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1 features ? programmable system clock with prescaler and five different clock sources ? 4-mhz crystal oscillator ? 32-mhz crystal oscillator ? rc-oscillator fully integrated ? rc-oscillator with external resistor adjustment ? external clock input wide supply-voltage range (2.2 v to 6.2 v) very low halt current (< 1 a) 4-kbyte rom, 256 4-bit ram 8 hard and software interrupt priority levels up to 10 external and 4 internal interrupts, bit wise maskable with programmable priority level up to 34 i/o lines including 8 high drive i/o-lines (20 ma, v dd = 5 v) i/o ports ? bit wise configurable with combined interrupt handling (for serial i/o applications) 2 8-bit multifunction timer/counters coded reset and watchdog timer (mask option) power-on reset and ?brown out? function various power-down modes efficient, hardware-controlled interrupt handling high level programming language qforth comprehensive library of useful routines windows 95/nt based development tools description the ATAR510 is a member of atmel?s family of 4-bit single-chip microcontrollers. it contains rom, ram, up to 34 digital i/o pins, up to 10 maskable external interrupt sources, 4 maskable internal interrupts, a watchdog timer, interval timer, 2 x 8-bit mul- tifunction timer/counter module, and a versatile software configurable on-chip system clock module. figure 1. block diagram marc4 system clock timer/ counter timer 0 timer 1 master reset te port 0 port 1 port 5 port b sclin i/o bus rom ram 4-bit cpu core 4k x 8 bit 256 x 4 bit watch- dog i/o i/o i/o test sleep nrst v dd v ss port 7 port a i/o port 4 i/o interrupt & reset prescaler av dd i/o i/o interrupt i/o interrupt port 6 real time clock oscin oscout melody & buzzer tim1 i/o port c 4 4 44 4 4 4 4 2 marc4 4-bit universal mirocontroller ATAR510 rev. 4703a?4bmcu?06/03
2 ATAR510 4703a?4bmcu?06/03 pin configuration figure 2. pinning sso44 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 s c l i n b p c 0 b p 0 0 b p 1 2 b p 1 1 b p 1 0 o s c i n o s c o u t b p 0 1 b p 0 2 b p 0 3 n r s t v s s v d d b p 4 3 b p 4 2 b p 4 1 b p 4 0 b p b 3 b p b 2 b p b 1 b p b 0 b p 7 0 b p 7 1 b p 7 2 b p 7 3 b p 5 3 b p 5 2 b p 5 1 b p 5 0 t i m 1 b p a 3 b p a 2 b p a 1 b p a 0 t e a v d d b p 6 1 b p 6 0 2 1 2 2 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 3 2 4 4 1 4 2 4 3 4 4 b p c 1 b p 1 3 v s s b p c 3 b p c 2 ATAR510 pin description pin symbol function 1 vss circuit ground 2 bp53 4 i/o lines of high current port 5 (1) ? bit wise configurable 3 bp52 4 i/o lines of high current port 5 (1) ? bit wise configurable 4 bp51 4 i/o lines of high current port 5 (1) ? bit wise configurable 5 bp50 4 i/o lines of high current port 5 (1) ? bit wise configurable 6 vdd power supply voltage +2.2 v to +6.2 v 7 bp43 (nbuz) high current i/o line bp43 of port 4 (1) ? configurable or buzzer output nbuz 8 bp42 (buz) high current i/o line bp42 of port 4 (1) ? configurable or buzzer output buz 9 bp41 (t0out1) i/o line bp41 of port 4 (1) ? configurable or timer/counter i/o t0out1 10 bp40 (t0out0) i/o line bp40 of port 4 (1) ? configurable or timer/counter i/o t0out0 11 bp03 4 i/o lines of port 0 ? automatic nibble wise configurable 12 bp02 4 i/o lines of port 0 ? automatic nibble wise configurable 13 bp01 4 i/o lines of port 0 ? automatic nibble wise configurable 14 bp00 4 i/o lines of port 0 ? automatic nibble wise configurable 15 tim1 dedicated i/o for timer 1 16 bpc1 4 i/o lines of port c (1) ? bit wise configurable i/o 17 te test mode input, used to control production test modes (internal pull-down) note: 1. for mask options, please see the order information.
3 ATAR510 4703a?4bmcu?06/03 18 bpc0 4 i/o lines of port c (1) ? bit wise configurable i/o 19 bp13 4 i/o lines of port 1 (1) ? automatic nibble wise configurable 20 bp12 4 i/o lines of port 1 (1) ? automatic nibble wise configurable 21 bp11 4 i/o lines of port 1 (1) ? automatic nibble wise configurable 22 bp10 4 i/o lines of port 1 (1) ? automatic nibble wise configurable 23 bpa3 4 i/o lines of port a (1) ? bit wise configurable, as inputs for port monitor module and optional coded reset inputs (1) 24 bpa2 4 i/o lines of port a (1) ? bit wise configurable, as inputs for port monitor module and optional coded reset inputs (1) 25 bpa1 4 i/o lines of port a (1) ? bit wise configurable, as inputs for port monitor module and optional coded reset inputs (1) 26 bpa0 4 i/o lines of port a (1) ? bit wise configurable, as inputs for port monitor module and optional coded reset inputs (1) 27 nrst reset input (/output), a logic low on this pin resets the device. an internal watchdog or coded reset can generate a low pulse on this pin 28 oscout 32-khz or 4-mhz quartz crystal output pin 29 oscin 32-khz or 4-mhz quartz crystal input pin 30 av dd analog power supply voltage +2.2 v to +6.2v 31 bpc2 4 i/o lines of port c (1) ? bit wise configurable i/o 32 bpc3 4 i/o lines of port c (1) ? bit wise configurable i/o 33 bpb0 4 i/o lines of port b (1) ? bit wise configurable i/o and as inputs for port monitor module 34 bpb1 4 i/o lines of port b (1) ? bit wise configurable i/o and as inputs for port monitor module 35 bpb2 4 i/o lines of port b (1) ? bit wise configurable i/o and as inputs for port monitor module 36 bpb3 4 i/o lines of port b (1) ? bit wise configurable i/o and as inputs for port monitor module 37 bp60 2 i/o lines of port 6 (1) ? bit wise configurable i/o or as external programmable interrupts 38 bp61 2 i/o lines of port 6 (1) ? bit wise configurable i/o or as external programmable interrupts 39 sclin external trimming resistor or external clock input 40 vss supply voltage 41 bp73 4 i/o lines of high current port 7 (1) ? bit wise configurable 42 bp72 4 i/o lines of high current port 7 (1) ? bit wise configurable 43 bp71 4 i/o lines of high current port 7 (1) ? bit wise configurable 44 bp70 4 i/o lines of high current port 7 (1) ? bit wise configurable pin description pin symbol function note: 1. for mask options, please see the order information.
4 ATAR510 4703a?4bmcu?06/03 marc4 architecture general description the marc4 microcontroller consists of an advanced stack-based 4-bit cpu core and on-chip peripherals. the cpu is based on the harvard architecture with physically sep- arate program memory (rom) and data memory (ram). three independent buses, the instruction bus, the memory bus and the i/o bus, are used for parallel communication between rom, ram and peripherals. this enhances program execution speed by allowing both instruction prefetching, and a simultaneous communication to the on-chip peripheral circuitry. the extremely powerful integrated interrupt controller with associ- ated eight prioritized interrupt levels supports fast and efficient processing of hardware events. the marc4 is designed for the high-level programming language qforth. the core includes both an expression and a return stack. this architecture enables high-level language programming without any loss of efficiency or code density. figure 3. marc4 core components of marc4 core the core contains rom, ram, alu, a program counter, ram address registers, an instruction decoder and an interrupt controller. the following sections describe each functional block in more detail. rom the program memory (rom) is mask programmed with the customer application pro- gram during the fabrication of the microcontroller. the rom is addressed by a 12-bit wide program counter, thus predefining a maximum program bank size of 4 kbytes. an additional 1 kbyte of rom exists which is used partly for a quality control self-test pro- gram. the remaining space ia available for the application program. the access to this additional rom section is done by using a rom-bank switch. the lowest user rom address segment is taken up by a 512-byte zero page which con- tains predefined start addresses for interrupt service routines and special subroutines accessible with single byte instructions (scall). the corresponding memory map is shown in figure 4. look-up tables of constants can also be held in rom and are accessed via the marc4?s built-in table instruction. instruction decoder ccr tos alu ram pc rp sp x y program 256 x 4-bit marc4 core clock reset sleep memory bus i/o bus instruction bus reset system clock interrupt controller on-chip peripheral modules memory
5 ATAR510 4703a?4bmcu?06/03 rom banking bank switching is fully supported by the compiler for customers programming with qforth. the marc4 switches from one rom bank to another by writing the new bank number to the rom bank register (rbr). conventional program space (power-up bank) resides in rom bank 0. each rom bank consists of a 4-kbyte address space whereby the lowest 2 kbyte is common to all banks, so that addresses between 000h and 7ffh always accesses the same rom data (see figure 4). when rom banking is used, the compiler will, if necessary, insert the program code to save and restore the condition of the rbr on bank switching. figure 4. rom map ram the marc4 contains 256 x 4-bit wide static random access memory (ram). it is used for the expression stack, the return stack and data memory for variables and arrays. the ram is addressed by any of the four 8-bit wide ram address registers sp, rp, x and y. figure 5. ram map rom bank 0 (2k x 8 bit) basebank zero page (not available) bank 1 (1k x 8 bit) fffh 7ffh 1ffh 000h fffh bffh 7ffh common base bank address area 1f0h 1f8h 010h 018h 000h 008h 020h 1e8h 1e0h scall addresses 140h 180h 040h 0c0h 008h $autosleep $reset int0 int1 int2 int3 int4 int5 int6 int7 1e0h 1c0h 100h 080h zero page 000h ram fch 00h autosleep ffh 03h 04h x y sp rp tos-1 expression stack return stack global variables ram address register: 07h (256 x 4-bit) global variables 4-bit tos tos-1 tos-2 30 sp expression stack return stack 0 11 12-bit rp v
6 ATAR510 4703a?4bmcu?06/03 expression stack the 4-bit wide expression stack is addressed with the expression stack pointer (sp). all arithmetic, i/o and memory reference operations take their operands from, and return their results to the expression stack. the marc4 performs the operations with the top of stack items (tos and tos-1). the tos register contains the top element of the expres- sion stack and works in the same way as an accumulator. this stack is also used for passing parameters between subroutines and as a scratch pad area for temporary stor- age of data. return stack the 12-bit wide return stack is addressed by the return stack pointer (rp). it is used for storing return addresses of subroutines, interrupt routines and for keeping loop index counts. the return stack can also be used as a temporary storage area. the marc4 instruction set supports the exchange of data between the top elements of the expression stack and the return stack. the two stacks, within the ram, have a user definable location and maximum depth. registers the marc4 controller has seven programmable registers and one condition code regis- ter. they are shown in the following programming model. program counter (pc) the program counter is a 12-bit register which contains the address of the next instruc- tion to be fetched from the rom. instructions currently being executed are decoded in the instruction decoder to determine the internal micro-operations. for linear code (no calls or branches) the program counter is incremented with every instruction cycle. if a branch, call, return instruction or an interrupt is executed, the program counter is loaded with a new address. the program counter is also used with the table instruction to fetch 8-bit wide rom constants. figure 6. programming model tos ccr 0 3 0 3 0 7 0 7 0 7 0 11 rp sp x y pc -- b i program counter return stack pointer expression stack pointer ram address register (x) ram address register (y) top of stack register condition code register carry/borrow branch interrupt enable reserved 0 7 00 c 0 rom bank register rbr -- -- bank
7 ATAR510 4703a?4bmcu?06/03 rom banking register (rbr) the rom banking register is a 4-bit register whereby in the ATAR510, only bit 2 is used. this indicates which rom bank is presently being addressed. the rbr is accessed with a standard qforth peripheral read or write instruction (in or out, port address ?d? hex). ram address registers the ram is addressed with the four 8-bit wide ram address registers: sp, rp, x and y. these registers allow access to any of the 256 ram nibbles. expression stack pointer (sp) the stack pointer contains the address of the next-to-top 4-bit item (tos-1) of the expression stack. the pointer is automatically pre-incremented if a nibble is moved onto the stack or post-decremented if a nibble is removed from the stack. every post-decre- ment operation moves the item (tos-1) to the tos register before the sp is decremented. after a reset the stack pointer has to be initialized with >sp s0 to allocate the start address of the expression stack area. return stack pointer (rp) the return stack pointer points to the top element of the 12-bit wide return stack. the pointer automatically pre-increments if an element is moved onto the stack, or it post- decrements if an element is removed from the stack. the return stack pointer incre- ments and decrements in steps of 4. this means that every time a 12-bit element is stacked, a 4-bit ram location is left unwritten. this location is used by the qforth compiler to allocate 4-bit variables. after a reset the return stack pointer has to be initial- ized via >rp fch. ram address registers (x and y) the x and y registers are used to address any 4-bit item in the ram. a fetch operation moves the addressed nibble onto the tos. a store operation moves the tos to the addressed ram location. by using either the pre-increment or post-decrement address- ing mode arrays in the ram can be compared, filled or moved. top of stack (tos) the top of stack register is the accumulator of the marc4. all arithmetic/logic, memory reference and i/o operations use this register. the tos register receives data from the alu, rom, ram or i/o bus. condition code register (ccr) the 4-bit wide condition code r egister contains the branch, the carry and the interrupt enable flag. these bits indicate the current state of the cpu. the ccr flags are set or reset by alu operations. the instructions set_bcf, tog_bf, ccr! and di allow direct manipulation of the condition code register. carry/borrow (c) the carry/borrow flag indicates that the borrow or carry out of the arithmetic logic unit (alu) occurred during the last arithmetic operation. during shift and rotate operations, this bit is used as a fifth bit. boolean operations have no affect on the c-flag. branch (b) the branch flag controls the conditional program branching. should the branch flag have been set by a previous instruction, a conditional branch will cause a jump. this flag is affected by arithmetic, logic, shift, and rotate operations. interrupt enable (i) the interrupt enable flag globally enables or disables the triggering of all interrupt rou- tines with the exception of the non-maskable reset. after a reset or while executing the di instruction, the interrupt enable flag is reset, thus disabling all interrupts. the core will not accept any further interrupt requests until the interrupt enable flag has been set again by either executing an ei or sleep instruction.
8 ATAR510 4703a?4bmcu?06/03 alu the 4-bit alu performs all the arithmetic, logical, shift and rotate operations with the top two elements of the expression stack (tos and tos-1) and returns the result to the tos. the alu operations affect the carry/borrow and branch flag in the condition code register (ccr). figure 7. alu zero-address operations instruction set the marc4 instruction set is optimized for the high level programming language qforth. many marc4 instructions are qforth words. this enables the compiler to generate a fast and compact program code. the cpu has an instruction pipeline allow- ing the controller to prefetch an instruction from rom at the same time as the present instruction is being executed. the marc4 is a zero-address machine, the instructions contain only the operation to be performed and no source or destination address fields. the operations are implicitly performed on the data placed on the stack. there are one and two byte instructions which are execut ed within 1 to 4 machine cycles. a marc4 machine cycle is made up of two system clock cycles (syscl). most of the instructions are only one byte long and are executed in a single machine cycle. for more information refer to the ?marc4 programmer?s guide?. i/o bus the i/o ports and the registers of the peripheral modules are i/o mapped. all communi- cation between the core and the on-chip peripherals takes place via the i/o bus and the associated i/o control. with the marc4 in and out instructions the i/o bus allows a direct read or write access to one of the 16 primary i/o addresses. more about the i/o access to the on-chip peripherals is described in the section ?peripheral modules?. the i/o bus is internal and is not accessible by the customer on the final microcontroller device, but it is used as the interface for the marc4 emulation (see also the section ?emulation?). interrupt structure the marc4 can handle interrupts with eight different priority levels. they can be gener- ated from the internal and external interrupt sources or by a software interrupt from the cpu itself. each interrupt level has a hard-wired priority and an associated vector for the service routine in the rom (see table 1). the programmer can postpone the processing of interrupts by resetting the interrupt enable flag (i) in the ccr. an interrupt occurrence will still be registered, but the interrupt routine only started after the i flag is set. all inter- rupts can be masked, and the priority individually software configured by programming the appropriate control register of the interrupting module (see section ?peripheral modules?). tos-1 ccr ram tos-2 sp tos-3 tos alu tos-4
9 ATAR510 4703a?4bmcu?06/03 interrupt processing for processing the eight interrupt levels, the marc4 includes an interrupt controller with two 8-bit wide interrupt pending and interrupt active registers. the interrupt controller samples all interrupt requests during every non-i/o instruction cycle and latches these in the interrupt pending register. whenever an interrupt request is detected, the cpu inter- rupts the program currently being executed, on condition that no higher priority interrupt is present in the interrupt active register. if the interrupt enable bit is set, the processor enters an interrupt acknowledge cycle. during this cycle a short call (scall) instruction to the service routine is executed and the current pc is saved on the return stack. an interrupt service routine is completed with the rti instruction. this instruction resets the corresponding bits in the interrupt pending/active register and fetches the return address from the return stack to the program counter. when the interrupt-enable flag is reset (triggering of interrupt routines are disabled), the execution of new interrupt ser- vice routines is inhibited but not the logging of the interrupt requests in the interrupt pending register. the execution of the interrupt is delayed until the interrupt-enable flag is set again. note that interrupts are only lost if an interrupt request occurs while the cor- responding bit in the pending register is still set (i.e., the interrupt service routine is not yet finished). it should also be noted that automatic stacking of the rbr is not carried out by the hard- ware and so if rom banking is used, the rbr must be stacked on the expression stack by the application program and restored before the rti. after a master reset (power-on, brown-out or watchdog reset), the interrupt-enable flag and the interrupt pending and interrupt active registers are all reset. interrupt latency the interrupt latency is the time from the occurrence of the interrupt to the interrupt ser- vice routine being activated. in marc4 this is extremely short (taking between 3 to 5 machine cycles depending on the state of the core). figure 8. interrupt handling 7 6 5 4 3 2 1 0 priority level int5 active int7 active int2 pending swi0 int2 active int0 pending int0 active int2 rti rti int5 int3 active int3 rti rti rti int7 time main/ autosleep main / autosleep
10 ATAR510 4703a?4bmcu?06/03 table 1. interrupt priority table table 2. hardware interrupts in the ATAR510, there are eleven hardware interrupt sources which can be pro- grammed to occupy a variety of priority levels. with the exception of the reset sources (rst), each source can be individually masked by mask bits in the corresponding con- trol registers. an overview of the possible hardware configurations is shown in table 2. software interrupts the programmer can generate interrupts by using the software interrupt instruction (swi) which is supported in qforth by predefined macros named swi0 to swi7. the software triggered interrupt operates exactly like any hardware triggered interrupt. the swi instruction takes the top two elements from the expression stack and writes the cor- responding bits via the i/o bus to the interrupt pending register. therefore, by using the swi instruction, interrupts can be re-prioritized or lower priority processes scheduled for later execution. interrupt priority rom address maskable interrupt opcode int0 lowest 040h yes c8h (scall 040h) int1 | 080h yes d0h (scall 080h) int2 | 0c0h yes d8h (scall 0c0h) int3 | 100h yes e8h (scall 100h) int4 | 140h yes e8h (scall 140h) int5 | 180h yes f0h (scall 180h) int6 | 1c0h yes f8h (scall 1c0h) int7 highest 1e0h yes fch (scall 1e0h) interrupt source possible interrupt priorities rst interrupt mask function 01234567 register bit nrst external x ? ? low level active watchdog # ? ? 1/2 to 2 s time out port a coded reset # ? ? level any inputs port a monitor * * * * paipr 3 any edge, any input port b monitor * * * * pbipr 3 any edge, any input port 60 external * * * * p6cr 1.0 any edge port 61 external * * * * p6cr 3.2 any edge interval timer inta * * itipr 0 1 of 8 frequencies (8 to 128 hz) interval timer intb * * itipr 1 1 of 8 frequencies (8 to 8192 hz) timer 0 * * * * t0cr 0 overflow/compare/ end measurement timer 1 * * * * t1cr 0 compare x = hardwired (neither optional or software configurable) # = customer mask option (see ?ordering information?) * = software configurable (see ?peripheral modules? section for further details)
11 ATAR510 4703a?4bmcu?06/03 master reset the master reset forces the cpu into a well-defined condition. it is unmaskable and is activated independent of the current program stat e. it can be triggered by either initial supply power-up, a short collapse of the power supply, a watchdog time-out, activation of the nrst input, or the occurence of a coded reset on port a (see figure 9). a master reset activation will reset the interrupt enable flag, the interrupt pending regis- ters the interrupt active registers and initializes all on-chip peripherals. when the reset condition disappears, the cpu remains reset for a further reset delay time (approximately 80 ms), after which it continues with a short call instruction (opcode c1h) to the rom address 008h. this activates the initialization routine $reset which in turn initializes all necessary ram variables, stack pointers and peripheral configuration registers. figure 9. reset configuration power-on reset the fully integrated power-on reset circuit ensures that the core is held in a reset state until the minimum operating supply voltage has been reached. a reset condition is also generated should the supply voltage drop momentarily below the minimum operating supply. external reset (nrst) an external reset can be triggered with the nrst pin. to activate an external reset, the pin should be low for a minimum of 4 s. port a port a i/o reset code cpu nrst v watch- power-on reset cpu reset rst pull-up code * time out v v wd reset * = mask option dog * dd ss dd reset delay timer
12 ATAR510 4703a?4bmcu?06/03 coded reset (port a) the coded reset circuit is connected direct ly to port a terminals. by using a mask option, the user can define a hardwired code combination (e.g., all pins low) which, if occurring on port a, will generate a reset in the same way as the nrst pin. table 3. multiple key reset options note: if this option is used, the reset is not maskable and will also trigger if the predefined code is written on to port a by the cpu itself. care should also be taken not to generate an unwanted reset by inadvertently passing through the reset code on input transitions. this applies especially if the pins have a high capacitive load. watchdog reset the watchdog?s function can be enabled vi a a mask option and triggers a reset with every watchdog counter overflow. to suppress the watchdog reset, the counter must be regularly reset by reading the watchdog register address (cwd). the cpu reacts in exactly the same manner as a reset stimulus from any of the above sources. clock generation clock module the clock module generates two clocks. the system clock (syscl) supplies the cpu and the peripherals while the lower frequency periphery sub-clock (subcl) supplies only the peripherals. the modes for clock sources are programmable with the os1-bit and os0 bit in the sc register and the ccs-bit in the cm-register. the ATAR510 contains a clock module with 4 different internal oscillator types: two rc- oscillators, one 4-mhz crystal oscillator and one 32-khz crystal oscillator. the pins osc1 and osc2 provide the interface to connect a crystal either to the 4-mhz, or to the 32-khz crystal oscillator. sclin can be used as an input for an external clock or to con- nect an external trimming resistor for the rc-oscillator 2. all necessary components with the exception of the crystal and the trimming resistor is integrated on-chip. any one of these clock sources can be selected to generate the system clock (syscl). in applications that do not requi re exact timing, it is possib le to use the fully integrated rc-oscillator 1 without any external components. the rc-oscillator 2 is more stable but the oscillator frequency must be trimmed with an external resistor attached between sclin and v dd . in this configuration, for system clock frequencies below 2 mhz, the rc-oscillator 2 frequency can be maintained stable with a tolerance of 10% over the full operating temperature and voltage range. the clock module is software programmable using the clock management register (cm) and the system configuration register (sc). the required oscillator configuration can be selected with the os(1:0)-bits in the sc-register. a programmable 4-bit divider stage allows the adjustment of the system clock speed. a synchronization stage avoids any clock glitches which could be caused by clock source switching. no_rst not used (default) rst2 bpa0 and bpa1 = low rst3 bpa0 and bpa1 and bpa2 = low rst4 bpa0 and bpa1 and bpa2 and bpa3 = low rst5 bpa0 and bpa1 = high rst6 bpa0 and bpa1 and bpa2 = high rst7 bpa0 and bpa1 and bpa2 and bpa3 = high
13 ATAR510 4703a?4bmcu?06/03 the cpu always requires syscl clocks to execute instructions, process interrupts and enter or leave the sleep state. internal oscillators are, depending on the condition of the nstop-bit automatically stopped and started where necessary. special care must however be taken when using an external clock source which is gated by one of the microcontroller port signals. this configurat ion can hang up if the external oscillator is switched off while the external clock source is still selected. it is therefore advisable in such a case to switch first to the internal rc-oscillator 1 source using the css-bit. the external source can then be reselected later when the external oscillator has again been restarted. figure 10. clock module table 4. clock modes ext. clock exin exout stop rc-oscillator2 rcout2 stop r trim 4-mhz oscillator 4out stop oscin oscout 32-khz oscillator 32out oscin oscout rc- oscillator 1 rcout1 control stop in1 in2 /2 /2 /2 /2 divider chain sleep stop nstop ccs css1 css0 cm: os1 os0 subcl syscl sc: * oscin * oscout * mask option 32 khz sclin syscl max /8 syscl max /64 rc[1:0] sc: to cpu and timer/ counter mode os1 os0 clock source for syscl clock source for subcl ccs = 1 ccs = 0 ccs = 1 ccs = 0 111 rc-oscillator 1 (internal) external input clock sycl max /64 sclin/128 201 rc-oscillator 1 (internal) rc-oscillator 2 with external trimming resistor sycl max /64 sycl max /64 310 rc-oscillator 1 (internal) 4-mhz oscillator sycl max /64 f xtal /128 400 rc-oscillator 1 (internal) 32-khz oscillator 32 khz
14 ATAR510 4703a?4bmcu?06/03 oscillator circuits and external clock input stage rc-oscillator 1 fully integrated for timing insensitive applications, it is possible to use the fully integrated rc-oscillator 1. it operates without any external components and saves additional costs. the rc-oscillator 1 center frequency tolerance is better than 50% over the full temperature and voltage range. a reduction in the application operating supply voltage and temperature ranges will result in impr oved frequency tolerance. for more detailed information see figures 53 - 55. the basic center frequency of the rc-oscillator 1 is pro- grammable with the rc1 and the rc0-bits in the sc-register. figure 11. rc-oscillator 1 external input clock the sclin pin can be driven by an external clock source provided it meets the specified duty cycle, rise and fall times and input levels. the maximum system clock frequency f sysclmax that the core can operate is f sclin /2 (see figure 10). figure 12. external input clock rc-oscillator 2 with external trimming resistor the rc-oscillator 2 is a high stbility oscill ator whereby the osci llator frequency can be trimmed with an external resistor between sclin and v dd . in this configuration, as long as the system clock frequency does not ex ceed 2 mhz, the rc-oscillator 2 frequency can be maintained stable with a tolerance of 10% over the full operating temperature and voltage range. for example: a syscl max frequency of 2 mhz, can be obtained by connecting a resis- tor r ext = 150 k (see figures 13, 50, 51 and 52). figure 13. rc-oscillator 2 rc- oscillator 1 rcout1 stop control rcout1 osc-stop rc1 rc0 ext. input clock exout stop ext. clock exout osc-stop exin sclin rc- oscillator 2 rcout2 stop rcout2 osc-stop r trim sclin r ext v dd
15 ATAR510 4703a?4bmcu?06/03 4-mhz oscillator the integrated system clock oscillator requires an external crystal or ceramic resonator connected between the oscin and oscout pins to establish oscillation. all the neces- sary oscillator circuitry, with the except ion of the actual crystal, resonator and the optional c3 and c4 are integrated on-chip. figure 14. system clock oscillator 32-khz oscillator some applications require accurate long-term time keeping without putting excessive demands on the cpu or alternatively low resolution computing power. in this case, the on-chip ultra low power 32-khz crystal oscillator can be used to generate both the subcl and/or the syscl. in this mode, power consumption can be significantly reduced. the 32-khz crystal oscillator will key operating (not stopped) during any cpu power-down/sleep mode. figure 15. 32-khz crystal oscillator 4-mhz oscillator 4out stop 4out osc-stop oscin oscout * oscin c1 * c2 oscout cer. res * mask o p tion c3 c4 xtal 32-khz oscillator 32out 32out oscin oscout * oscin c1 * c2 oscout xtal 32 khz * mask o p tion
16 ATAR510 4703a?4bmcu?06/03 clock management the clock management register controls t he system clock divider and synchronization stage. writing to this register triggers the synchronization cycle. clock management register (cm) auxiliary register address: ?e?hex auxiliary register address: ?e?hex bit 3 bit 2 bit 1 bit 0 cm: nstop ccs css1 css0 reset value: 1111b nstop n ot stop peripheral clock nstop = 0, stops the peripheral clock (subcl) while the core is in sleep mode, 32-khz crystal oscillator subcl clock cannot be stopped nstop = 1, enables the peripheral clock (subcl) while the core is in sleep mode ccs c ore c lock s elect ccs = 1, the internal rc-oscillator 1 generates syscl ccs = 0, the 4-mhz crystal oscillator, the 32-khz crystal oscillator, an external clock source or the internal rc-oscillator 2 (with the external resistor) will generate syscl dependent on the setting of os0 and os1 in the system configuration register css(1:0) c ore s peed s elect these two bits control the system clock divider chain css1 css0 divider note 0 0 16 syscl max /8 0 1 8 syscl max /4 1 0 4 syscl max /2 112 reset value = syscl max
17 ATAR510 4703a?4bmcu?06/03 system configuration register (sc) primary register address: ?e?hex if ccs = 0 in the cm-register, the rc-oscillator 1 is stopped. power-down modes the ATAR510 encorporates several modes which enable the power consumption to be tailored to a minimum without sacrificing computational power. when the controller exits the lowest priority interrupt task, it reverts to a sleep state. this is a cpu shut- down condition which is used to reduce average system power consumption where the cpu itself is only partially utilized. in sleep, the cpu clocking system is deactivated whereby the peripherals and associated clock sources may remain active (standby mode) or they can also be halted (halt mode). in standby mode, the peripherals are able to continue operation and if required also generate interrupts which can, along with a reset reactivate the cpu to bring it out of the sleep state. sleep can only be maintained when none of the interrupt pending or active register bits are set. the application of the $autosleep routine ensures the correct function of the sleep mode. in both standby and active modes the current consumption is largely dependent on the frequency of the cpu system clock (syscl) and the supply voltage (vdd) (see figure 48 and figure 49) while the halt mode current is merely controller static leakage current. selection of standby or halt mode is performed by the nstop bit in the clock manage- ment register (cm). it should be noted that the low power 32-khz crystal oscillator, if enabled will always remain active in both standby and halt modes. bit 3bit 2bit 1bit 0 sc: write rc1 rc0 os1 os0 reset value: 1111b rc1, rc0 internal rc oscillator 1 frequency selection (syscl max ) rc1 rc0 syscl max at 25 c, v dd = 5 v note 007.0 mhz (f irc0 )? 013.0 mhz (f irc1 )? 102.0 mhz (f irc2 )? 110.8 mhz (f irc3 ) reset value os1, os0 oscillator selection bits (in conjunction with the ccs-bit) ccs os1 os0 subcl system oscillator selection 0 1 1 external input clock at sclin 0 0 1 syscl max /64 rc-oscillator 2 with r ext 0 1 0 4-mhz crystal oscillator 0 0 0 32 khz 32-khz crystal oscillator 1 x x syscl max /64 or 32 khz rc-oscillator 1
18 ATAR510 4703a?4bmcu?06/03 table 5. power-down modes clock monitor mode figure 16. clock monitoring for trimming purposes, the ATAR510 can be put into a clock monitor mode. by forcing the test input (te) high, the syscl clock will appear on bp11 (port 1, bit 1) and subcl clock on port bp10 (port 1, bit 0). on re leasing the te pin, the bp10 and bp11 will resume their normal function (see figure 16). peripheral modules addressing peripherals accessing the peripheral modules takes place via the i/o bus (see figure 17). the in or out instructions allow direct addressing of up to 16 i/o modules. a dual register addressing scheme has been adopted which addresses the "primary register" directly. to address the auxiliary register, the access must be switched with an "auxiliary switch- ing module". thus, a single in (or out) to the module address will read (or write) into the module primary register. accessing the auxiliary register is performed with the same instruction preceded by writing the module address into the auxiliary switching module. byte-wide registers are accessed by multiple in (or out) instructions. extended addressing is used for more complex peripheral modules, with a larger number of regis- ters. in this case, a bank of up to 16 subport registers are indirectly addressed with the subport address being initially written into the auxiliary register. please refer to the 'hardc510.scr' hardware interface file as a programming guideline. mode cpu core state nstop rc-oscillator 1 rc-oscillator 2 4-mhz oscillator 32-khz oscillator external input clock at sclin active run 1 run run enabled standby sleep 1 run run enabled halt sleep 0 stop run disabled syscl clocks nrst te bp11 oscillator su p ervisor y mode normal operation bp10 subcl clocks
19 ATAR510 4703a?4bmcu?06/03 figure 17. example of i/o addressing aux. . eg r subport 0 subport 1 subport fh su por bt eh i/o bus aux. reg. primary reg. bank of primary regs. primary reg. primary reg. (address pointer) auxiliary switch module i n d i r e c t s u b p o r t a c c e s s d u a l r e g i s t e r a c c e s s s i n g l e r e g i s t e r a c c e s s to other modules module m1 module asw module m2 module m3 a ddr ess( m 2) a d dr ess( a sw ) o u t a ux ._d ata a ddr ess( m 2) o u t prim._data a ddress(m 2) ou t (pr i mar y regi st er wr i t e) prim._data a ddress(m 3) out (primary register write) a ddr.(m 1) a ddr.(a sw ) ou t a ddr.( sport) a ddr.(m 1) ou t 1 2 (subpor t regi st er wr i te) sport_data a ddr.(m 1) out 3 4 5 6 1 2 3 4 7 7 5 6 example of qforth pr ogram code addr.(mx) = module mx address a ux._d ata = data to be wr itten i nto auxil i ary regi ster pr im ._d at a = data to be wr i tten i nto pri mar y register . addr.(asw) = auxi l iar y switch m odule addr ess sport_data(lo) = data to be written into subport (l ow nibble) sport_data(hi) = data to be written into subport (high nibble) a ddr.(sport) = subpor t addr ess a ux._d ata (lo)= data to be wr itten into auxi l iar y register (low ni bble) a ux . _d at a ( hi ) = data to be written into auxiliary register(high nibbl e) a ddr.(m 1) a ddr.(a sw ) out a ddr.(sport) a ddr.(m 1) out 1 2 (subpor t regi ster read) a ddr.(m 1) in a ddress(m 2) a ddress(a sw) out a ddress(m 2) i n (auxiliary register read) 5 6 a ddr ess(m 2) i n (primary register read) 4 a ddress(m 1) a ddress(a sw ) out a ddress(m 1) i n (auxiliary register read) 1 2 a d dr ess( m 3 ) i n (pri mary regi ster read) 7 a ddr.(m 1) a ddr.(a sw ) ou t a ddr.( sport) a ddr.(m 1) ou t 1 2 (subpor t regi ster wr i te byte) sport_data(lo) addr.(m 1) out 3 a ddr.(m 1) a ddr.(a sw ) out a ddr.(sport) a ddr.(m 1) out 1 2 (subpor t register read byte) a ddr.(m 1) i n 3 sport_data(hi) addr.(m 1) out 3 a ddr.(m 1) in 3 a ddress(m 2) a ddress(a sw) out a ux._data(lo) a ddress(m 2) out (a uxiliary register write byte) 5 6 a ux ._d at a(hi ) a ddr ess( m 2) o u t 6 3 ( auxiliary register write )
20 ATAR510 4703a?4bmcu?06/03 table 6. peripheral addresses port address name write/read reset value register function module type see page 0 p0dat w/r 1111b port 0 - data register/input data m3 22 1 p1dat w/r 1111b port 1- data register/input data m3 22 2 paipr w 1111b port a - interrupt priority register m2 24 auxiliary paicr w 1111b port a - interrupt control register 24 3 cwd r ? watchdog timer reset m3 32 pbibr w 1111b port b- interrupt priority register m2 24 auxiliary pbicr w 1111b port b- interrupt control register 24 4 p4dat w/r 1111b port 4 - data register/pin data m2 22 auxiliary p4ddr w 1111b port 4 - data direction register 22 5 p5dat w/r 1111b port 5 - data register/pin data m2 22 auxiliary p5ddr w 1111b port 5 - data direction register 22 6 p6dat w/r 0011b port 6 - data register/pin data m2 27 auxiliary p6cr w 1111 1111b port 6 - control register (byte) 27 7 p7dat w/r 1111b port 7- data register/pin data m2 22 auxiliary p7ddr w 1111b port 7- data direction register 22 8 asw w 1111b auxiliary switch register asw 19 9 tcm w/r 1111b data to/from subport addressed by tcsub m1 19 auxiliary t0sr r 0000b timer 0 interrupt status register m1 38 tcsub w 1111b timer/counter subport address pointer m1 33/34 subport address 0 t0mo w 1111b timer 0 mode register m1 38 1 t0cr w 1111b timer 0 control register m1 39 2 t1m0 w 1111b timer 1 mode register m1 47 3 t1cr w 1111b timer 1 control register m1 47 4 tcmo w 1111b timer/counter mode register m1 36 5 tcior w 1111b timer/counter i/o control register m1 35 6 tccr w 1111b timer/counter control register m1 35 7 tcip w 1111b timer/counter interrupt priority m1 34 8 t1cp w xxxx xxxxb timer 1 compare register (byte) m1 48 t1ca r xxxx xxxxb timer 1 capture register (byte) m1 9 t0cp w xxxx xxxxb timer 0 compare register (byte) m1 40 t0ca r xxxx xxxxb timer 0 capture register (byte) m1 a bzcr w 1111b buzzer control register m1 51 b-f ? reserved a padat w/r 1111b port a - data register/pin data m2 22 auxiliary paddr w 1111b port a - data direction register 22 b pbdat w/r 1111b port b - data register/pin data m2 22 auxiliary pbddr w 1111b port b - data direction register 22 c pcdat w/r 1111b port c - data register/pin data m2 22 auxiliary pcddr w 1111b port c - data direction register 22 d rbr w 0000b rom bank switch register m3 7 e sc w 1111b system configuration register m2 17 auxiliary cm w/r 1111b clock management register 16 f itfsr w 1111b interval timer frequency select register m2 31 auxiliary itfsr w 1111b interval timer interrupt priority register 30
21 ATAR510 4703a?4bmcu?06/03 bi-directional ports table 7. overview of port features notes: 1. either "open drain down", "open drain up" or cmos output configuration 2. this output must always be cmos 3. the dynamic pull-up/-down transistors are mask programmable and if programmed, are only activated when the associated complementry driver transistor is off. ie. a dynamic pull-up transistor is only active when the port is either in input mode (b oth drivers off) or when a logical 1 is written to the port pad (low driver off) in output mode (figure 19) 4. the static pull-up/-down transitors are mask programmed and if programmed are always active independant of the port direction or driven state (figure 19) for further data see section ?dc operating characteristics?. all ports (0, 1, 4, 5, 7, a, b and c with the exception of port 6) are 4 bits wide. port 6 has a data width of only 2 bits (bit 0 and bit 1). the ports may be used for data input or out- put. all ports that can either directly or indirectly generate an interrupt are equipped with schmitt trigger inputs. a variety of mask options are available such as open drain, open source and full complementary outputs as well as different types of pull-up and pull- down transistors. all port data registers (pxdat) are i/o mapped to the primary address register of the respective port address, and the port data direction register (pxddr) to the corresponding auxiliary register. all bi-directional ports except port 0 and port 1, include a bit wise- programmable data direction register (pxddr) which allows the individual programming of each port bit as input or output. it is also possible to read the pin condition when in output mode. this is a useful feature for self-testing and for collision detection on wired-or bus systems. there are five different types of bi-directional ports: ports 0 and 1: 4-bit wide, bi-directional ports with automatic full bus width direction switching port 4: 4-bit wide, bit wise programmable bi-directional port also provides the i/o interface to timer 0 and the buzzer ports 5, 7 and c: 4-bit wide, bit wise programmable high drive i/o ports port 6: 2-bit wide, bit wise programmable bi-directional port with optional static (4 k ) pull-up/-down and programmable interrupt logic ports a and b: 4-bit wide, bit wise programmable bi-directional ports with optional port monitor function port address 014567abc number of bits 444424444 bit wise programmable direction no no yes yes yes yes yes yes yes output drivers mask configurable (1) no (2) yes yes yes yes yes yes yes yes dynamic pull-up/-down typ. (ohm) (3) 500k 500k 500k 500k 500k 500k 500k 500k 500k static pull-up/-down typ. (ohm) (4) none none 30k 30k 4k 30k 30k 30k 30k schmitt trigger inputs yes yes yes no yes no yes yes no additional functions timer 0 external interrupt port monitor/ coded reset port monitor
22 ATAR510 4703a?4bmcu?06/03 port data register (pxdat) primary register address: ?port address? hex * bit 3 msb, bit 0 lsb, x port address port data direction register (pxddr) auxiliary register address: ?port address? hex table 8. port data direction register (pxddr) bi-directional port 0 and port 1 in this port type, the data direction register is not independently software programmable because the direction of the complete po rt is switched automatically when an i/o instruction occurs (see figure 18). the port can be switched to output mode with an out instruction and to input with an in instruction. the data written to a port will be stored in the output data latches and appears immediately at the port pin following the out instruction. after reset, all output latches are set to 1 and the ports are switched to input mode. an in instruction reads the condition of the associated pins. note: care must be taken when switching these bi-directional ports from output to input. the capacitive pin loading at this port, in conjunction with the high resistance pull-ups, may cause the cpu to read the contents of the output data register rather than the external input state. this can be avoided by using either of the following programming techniques: use two in instructions and drop the first data nibble. the first in switches the port from output to input and the drop removes the first invalid nibble. the second in reads the valid pin state. use an out instruction followed by an in instruction. with the out instruction, the capacitive load is charged or discharged depending on the optional pull-up /pull- down configuration. write a 1 for pins with pull-up resistors, and a 0 for pins with pull-down resistors. bit 3 * bit 2 bit 1 bit 0 pxdat pxdat3 pxdat2 pxdat1 pxdat0 reset value: 1111b bit 3 *bit 2bit 1bit 0 pxddr pxddr3 pxddr2 pxddr1 pxddr0 reset value: 1111b code: 3 2 1 0 function x x x 1 bpx0 in input mode x x x 0 bpx0 in output mode x x 1 x bpx1 in input mode x x 0 x bpx1 in output mode x 1 x x bpx2 in input mode x 0 x x bpx2 in output mode 1 x x x bpx3 in input mode 0 x x x bpx3 in output mode
23 ATAR510 4703a?4bmcu?06/03 figure 18. bi-directional port 0 and 1 bi-directional port 5, port 7 and port c all bi-directional ports except port 0 and port 1, include a bitwise programmable data direction register (pxddr) which allows the individual programming of each port bit as input or output. it also enables the reading of the pin condition in output mode. the bi-directional ports 5, 7 and c as well as port a and port b are equipped with the same standard i/o logic. however, port 5, port 7 and port c include standard cmos input stages, whereas port a, port b and all other digital signal pins have schmitt trigger inputs. port 5 and port 7 have high current output drive capability for up to 20 ma at 5 v. whereby the instantaneous sum of the output currents should not exceed 100 ma. figure 19. bi-directional ports 5, 7, a, b and c out in reset i/o bus d r s q q nq r master reset pxdaty (*) mask options (data out) (direction) port 1 only bpxy v dd pull-up pull-down v dd * * * * master reset q q bpxy mask options * * pxdaty pxddry i/o bus d i/o bus i/o bus * * pull-up pull-down v dd * static pull-up (data out) (direction) * s d * s v dd * static pull-down 30 k at 5 v port a and port b with schmitt trigger
24 ATAR510 4703a?4bmcu?06/03 bi-directional port a and port b with port monitor function figure 20. port monitor module of port a and port b in addition to the standard i/o functions described in section ?bi-directional port 5, port 7 and port c?, both port a (bpa3 - bpa0) and port b (bpb3 - bpb0) are equipped with schmitt trigger inputs and a port monitor modul e. this module is connected across all four port pins (see figure 20) and is intended for monitoring those pins selected by con- trol bits enx3 - enx0 and generating an interrupt when the first pin leaves a preselected logical default idle state. this state is defined by control bit itrx . transitions on other pins will only cause an interrupt if the other pins have first returned to the idle state. this, for example is useful for interrupt initiat ed port scanning without the power consuming task of continuously polling for port activity. using the port interrupt control register (p xicr), pins can be individually selected. a non-selected pin cannot generate an interrupt. the port interrupt priority register (pxipr) allows masking of each interrupt, definition of the interrupt edge and program- ming of the interrupt priority levels. when programming or reprogramming either of the port monitor control registers, any previously generated interrupt on that port which has not yet been acknowledged by the cpu or an interrupt generated by the reprogramming itself is automatically cleared. port a can also be used for a mask programmable coded reset. for more information see section ?hardware reset?. the port interrupt priority registers paipr and pbipr are i/o mapped to the the pri- mary address registers of the port monitor module addresses '2'h and '3'h respectively. the port interrupt control registers paicr and pbicr are mapped to the correspond- ing auxiliary registers. port monitor interrupt priority register (pxipr) pxicr bpx3 bpx2 bpx1 bpx0 decoder connected to ports a and b (x = a or b) int5 int7 int3 int1 int5 int7 int3 int1 pxipr enx3 enx2 enx1 enx0 imax itrx prx1 prx2 00 01 10 11 prx1 prx2 2:4 x = ?a? (port a) or ?b? (port b) (port a) primary register address: '2'hex (port b) primary register address: '3'hex bit 3 bit 2 bit 1 bit 0 pxipr imx itrx prx2 prx1 reset value: 1111b imx itrx prx2..1 - interrupt mask - interrupt transition - interrupt priority code
25 ATAR510 4703a?4bmcu?06/03 table 9. port monitor interrupt priority register (pxipr) port monitor interrupt control register (pxicr) table 10. port monitor interrupt control register (pxicr) code 3 2 1 0 function x x 0 0 port monitor interrupt priority 7 x x 0 1 port monitor interrupt priority 5 x x 1 0 port monitor interrupt priority 3 x x 1 1 port monitor interrupt priority 1 x 0 x x port monitor interrupt on falling edge x 1 x x port monitor interrupt on rising edge 0 x x x port monitor interrupt enabled 1 x x x port monitor interrupt disabled x = 'a' (port a) or 'b' (port b) (port a) primary register address: '2'hex (port b) primary register address: '3'hex bit 3 bit 2 bit 1 bit 0 pxicr enx3 enx2 enx1 enx0 reset value: 1111b enx3... 0 port monitor input enable code code 3 2 1 0 function x x x 0 bit 0 can generate an interrupt x x x 1 bit 0 cannot generate an interrupt x x 0 x bit 1 can generate an interrupt x x 1 x bit 1 cannot generate an interrupt x 0 x x bit 2 can generate an interrupt x 1 x x bit 2 cannot generate an interrupt 0 x x x bit 3 can generate an interrupt 1 x x x bit 3 cannot generate an interrupt
26 ATAR510 4703a?4bmcu?06/03 bi-directional port 6 figure 21. bi-directional port 6 this 2-bit bi-directional port can be used as a bitwise programmable i/o. the data is lsb aligned so that the two msb's will not appear on the port pins when written. the port pins can also be used as external interrupt inputs (see figure 21 and figure 22). both interrupts can be masked or independently configured to trigger on either edge. the interrupt priority levels are also configurable. the interrupt configuration and port direction is controlled by the port 6 control register (p6cr). an additional low resis- tance pull-up transistor (mask option) provi des an internal bus pull-up for serial bus applications. in output mode (pxddr bit = 0), the respective port data register (pxdat) bit appears on the port pin, driven by an output port driver stage which can be mask programmed as open drain, or full complementary cmos. with an in instruction the actual pin state can be read back into the controller at any time without changing the port directional mode. if the output port is mask configured as an open drain driver, the controller is able to receive the external data on this pin without switching into input mode as long as the output transistor is switched off. in input mode (pxddr bit = 1), the output driver stage is deactivated, so that an in instruction will directly read the pin state which can be driven from an external source. in this case, the state of the port data register (pxdat), although not appearing at the pin itself, remains unchanged. high resistance mask selectable pull-up or pull-down transis- tors are automatically switched onto the port pin in input mode. the port data register is written to the respective port address with an out instruction. the port 6 data register (p6dat) is i/o mapped to the primary address register of address '6'hex and the port 6 control register (p6cr) to the corresponding auxiliary register. the p6cr is a byte wide register a nd is written by writing the low nibble first and then the high nibble (see section "addressing peripherals?). master reset q v dd v dd bp6y mask options * * p6daty i/o bus d in enable i/o bus * * pull-up pull-down v dd * static pull-up (data out) * * s y = 0 or 1 strong 4k at 5 v * v dd static pull-down strong 4k at 5 v
27 ATAR510 4703a?4bmcu?06/03 port 6 data register (p6dat) port 6 control register (p6cr) table 11. port 6 control register (p6cr) primary register address: ?6?hex bit 3bit 2bit 1bit 0 p6dat not used not used p6dat1 p6dat0 reset value: xx11b the unused bits 2 and 3 are 0, if read. auxiliary register address: ?6?hex bit 3bit 2bit 1bit 0 p5cr first write cycle p61im2 p61im1 p60im2 p60im1 reset value: 1111b bit 7bit 6bit 5bit 4 second write cycle p61pr2 p61pr1 p60pr2 p60pr1 reset value: 1111b p6xim2, p6xim1 - port 6x interrupt mode/direction code p6xpr2, p6xpr1 - bp6x interrupt priority code auxiliary address: ?6?hex first write cycle second write cycle code 3 2 1 0 function code 3 2 1 0 function x x 1 1 bp60 in input mode - interrupt disabled x x 1 1 bp60 set to priority 1 x x 0 1 bp60 in input mode - rising edge interrupt x x 1 0 bp60 set to priority 3 x x 1 0 bp60 in input mode - falling edge interrupt x x 0 1 bp60 set to priority 5 x x 0 0 bp60 in output mode - interrupt disabled x x 0 0 bp60 set to priority 7 1 1 x x bp61 in input mode - interrupt disabled 1 1 x x bp61 set to priority 0 0 1 x x bp61 in input mode - rising edge interrupt 1 0 x x bp61 set to priority 2 1 0 x x bp61 in input mode - falling edge interrupt 0 1 x x bp61 set to priority 4 0 0 x x bp61 in output mode - interrupt disabled 0 0 x x bp61 set to priority 6
28 ATAR510 4703a?4bmcu?06/03 figure 22. port 6 external interrupts bi-directional port 4 the bi-directional port 4 is both a bit wise configurable i/o port and provides the external pins for both the timer 0 and the internal buzzer generator. as an i/o port, it performs in exactly the same way as bi-directional port 5, 7, a, b and c (see figure 19). two addi- tional multiplexers allow data and port direction control to be passed over to other internal modules (timer 0 or buzzer). each of the four port 4 pins can be individually switched by the timer/counter i/o register (tcio). figure 23 shows the internal inter- faces to port 4. figure 23. bi-directional port 4 bidir. port in_enable data in p6cr: bp60 bidir. port in_enable data in bp61 cr0 decode decode decode decode int6 int4 int2 int0 int7 int5 int3 int1 i/o bus cr7 cr6 0 1 0 0 0 1 11 int6 int4 int2 int0 cr5 cr4 0 1 0 0 0 1 11 int7 int5 int3 int1 cr3 cr2 0 1 0 0 0 1 11 dir. int edge int disabled dir. dir. edge edge mask mask cr1 cr0 out yes - yes in - in in no no cr7 cr6 cr5 cr4 cr3 cr2 cr1 master reset q v dd v dd bp4y mask options * * p4daty i/o bus d i/o bus i/o bus * * pull-up pull-down (data out) * * s p4ddry s q d tcioy t0out (direction) tdir t0in v dd * * pull-up v dd static pull-down static 30 k at 5 v
29 ATAR510 4703a?4bmcu?06/03 tim1 - dedicated timer 1 i/o pin figure 24. bi-directional pin tim1 tim1 is a dedicated bi-directional i/o stage for signal communication to and from timer 1 in the timer/counter module (see figure 24). it has no i/o bus interface and is not directly accessible from the cpu. direction control is performed from the timer/counter configuration registers. interval timers/prescaler the interval timers are based on a frequency divider for generating two independent time base interrupts. it is driven by subcl generated by the clock module (see figure 10) and consists of a 15-stage binary divider and two programmable multiplexers for selecting the appropriate interrupt frequencies for each interrupt source (see figure 25). each multiplexer is completely independent and is controlled by the common interval timer frequency select register (itfsr). buffer registers store the respective fre- quency select codes and ensure complete programming independence of each interrupt channel. interrupt masking and programming of the interrupt priority levels is performed with the aid of the interval timer interrupt priority register (itipr). t1in (timer 1 input) t1out (timer 1 output) t1dir (direction control) v dd v dd tim1 mask options * * * * pull-up pull-down * *
30 ATAR510 4703a?4bmcu?06/03 figure 25. interval timers/prescaler interval timer registers the interval timer frequency select register (itfsr) is i/o mapped to the primary address register of the prescaler/interval timer address ('f'hex) and the interval timer interrupt priority register (itipr) to t he corresponding auxiliary register. the interrupt masks mia and mib enable interrupt masking of inta and intb respectively. each interrupt source can be programmed with pra and prb to one of two interrupt priority levels. disabling both interrupts resets the interval timer. interval timer interrupt priority register (itipr) table 12. interval timer interrupt priority register (itipr) subcl ck 8092 hz 4096 hz 2048 hz 1024 hz 256 hz 128 hz 64 hz 32 hz 8 hz 4 hz 2 hz 1 hz 1 hz 0h 1h 2h 3h 4h 5h 6h 7h 2 hz 4 hz 8 hz 16 hz 16 hz 32 hz 64 hz 128 hz 8 hz 8h 9h ah bh ch dh eh fh 16 hz 64 hz 256 hz 1024 hz 2048 hz 4096 hz 8192 hz itfsr fs1 fs2 fs3 fs0 buffer buffer itipr mia pra prb mib inta 8:1 mux intb 8:1 mux int5 int1 int6 int2 r 15-stage binary counter 2 2 222 2 22 2 22 2 222 34 5 6 78 9 10 11 12 13 14 15 (e.g. subcl = 32 khz) auxiliary register address (write only): 'f'hex bit 3bit 2bit 1 bit 0 itipr prb pra mib mia reset value: 1111b prb - priority select interval timer interrupt intb pra - priority select interval timer interrupt inta mib - mask interval timer interrupt intb mia - mask interval timer interrupt inta code 3 2 1 0 function x x 1 1 reset prescaler and halt x x x 1 interrupt a disabled x x x 0 interrupt a enabled x x 1 x interrupt b disabled x x 0 x interrupt b enabled x 1 x x interrupt a => priority 1 x 0 x x interrupt a => priority 5 1 x x x interrupt b => priority 2 0 x x x interrupt b => priority 6
31 ATAR510 4703a?4bmcu?06/03 interval timer frequency select register table 13. interval timer frequency select register (itfsr) the control bit fs3 determines whether the inta or the intb buffer register is loaded with the select code (fs2-fs0). this allows independent programming of interval times for inta and intb. primary register address (write only): 'f'hex bit 3bit 2bit 1 bit 0 itfsr fs3 fs2 fs1 fs0 reset value: 1111b fs3... 0 - frequency select code code 3 2 1 0 function subcl divide by subcl = 32 khz 0 0 0 0 inta 2 15 select 1 hz 0 0 0 1 2 14 select 2 hz 0 0 1 0 2 13 select 4 hz 0 0 1 1 2 12 select 8 hz 0 1 0 0 2 11 select 16 hz 0 1 0 1 2 10 select 32 hz 0 1 1 0 2 9 select 64 hz 0 1 1 1 2 8 select 128 hz 1 0 0 0 intb 2 12 select 8 hz 1 0 0 1 2 11 select 16 hz 1 0 1 0 2 9 select 64 hz 1 0 1 1 2 7 select 256 hz 1 1 0 0 2 5 select 1024 hz 1 1 0 1 2 4 select 2048 hz 1 1 1 0 2 3 select 4096 hz 1 1 1 1 2 2 select 8192 hz
32 ATAR510 4703a?4bmcu?06/03 watchdog timer figure 26. watchdog timer the watchdog timer is a 17-stage binary divider clocked by subcl generated within the clock module (see figure 10 and figure 26). it can only be enabled as a mask option whereby it must be periodically reset from the application program. the program cannot disable the watchdog. if the cpu find itself for an extended length of time in sleep mode or in a section of program that includes no watchdog reset, then the watchdog will overflow, thus forcing the nrst pin low. this initiates a master reset. the timeout period can be set to 0.5, 1 or 2 seconds (if subcl = 32 khz) by using a mask option. to reset the watchdog, the program must perform an in-instruction on the address cwd ('3'hex). no relevant data is usually received. the operation is therefore normally followed by a drop to flush the data from the stack. timer/counter module (tcm) the tcm consists of two timer/counter blocks (timer 0 and timer 1) which can be used separately, or together as a single 16-bi t counter/timer (see figure 27 and figure 29). each timer can be supplied by various internal or external clock sources. these can be selected and divided under program control using the timer/counter control register (tccr), the timer 0 control register (t0cr) and the timer 1 control register (t1cr). capture and compare registers (t0ca,t1ca,t0cp and t1cp) not only allow event counting, but also the generation of various timed output waveforms including program- mable frequencies, modulated melody tones, pulse width modulated (pwm) and pulse density modulated (pdm) output signals. when in one of these signal generation modes, the capture register acts as timer shadow register, the current timer state is fro- zon whenever read by the cpu. timer 0 is further equipped to perform a variety of time measurement operations. in this mode the capture register is used together with the gat- ing logic for performing asynchronous, externally triggered snapshot measurements. these measurements include single input pulse width and period measurements and also dual input phase and positional measurements. the mode configuration is set in the timer 0 and timer 1 mode registers (t0mo and t1mo). each timer represents a single maskable interrupt source (t0int and t1int), the prior- ity of which can be configured under program control. a timer 0 interrupt can be caused by any of three conditions (overflow, compare or end-of-measurement). the associated status register (t0sr) differentiates between these. a status register is not necessary in timer 1 as an interrupt is caused only on a compare condition. 17-stage binary counter subcl ck rrrrrrrrrrrrrrrr r read wdres v * watchdog enable * * * * mask option 2 14 nrst master reset dd 2 15 2 16
33 ATAR510 4703a?4bmcu?06/03 figure 27. timer/counter module ck prescaler rst gating control mux 4:1 mux 8:1 clock control up/down up/down counter t0ca compare t0cp reload control t0cr t0mo reset capture register compare register output control t0sr status register end-of- measu- rement overflow int. enable int output control t1cp compare up/down counter t1ca compare register reload control carry t1mo clock control reset capture register mux 2:1 mux 8:1 t1cr rst prescaler ck mux 4:1 16-bit mode int int. enable tccr tcmo t0out0 t1out t0in1 t0in0 syscl subcl subcl syscl t1in t0out1 t0out0 t0int t1int t1out timer 0 timer 1 < = cpu read/write registers overflow
34 ATAR510 4703a?4bmcu?06/03 general timer/counter control registers with the exception of the timer 0 interrupt status register (t0sr), all the timer/counter registers are indirectly addressed using ex tended addressing as described in the sec- tion "addressing peripherals". an overview of all register and subport addresses is shown in table 6. the timer/counter auxiliary register (tcsub) holds the subport address of the particular register about to be accessed. care has to be taken to ensure that this subport access sequence is not interrupted. please refer to the 'hardc510.scr' hardware interface file as a programming guideline. timer/counter clock control register (tccr) table 14. timer/counter clock control register (tccr) note: 1. if tcio0 = low (connects timer 0 to port 4) the timer/counter clock control register (tccr) controls the clock source to both timer 0 and timer 1 prescalers. if an external clock source (on bp40 or tim1) is selected, then the corresponding port direction is automatically switched to input mode (see figure 27). note: the tcio0 bit must be set low for the bp40 external timer/counter access. timer/counter interrupt priority register (tcip) the timer/counter interrupt priority register (tcip) is used to configure timer 0 and timer 1 interrupt priority levels. subport address (indirect write access): '6'hex of port address '9'hex bit 3bit 2bit 1 bit 0 tccr t1cl2 t1cl1 t0cl2 t0cl1 reset value: 1111b t0cl2, t0cl1 - timer 0 clock source select t1cl2, t1cl1 - timer 1 clock source select code 3 2 1 0 function direction (tdir) bp40 (1) tim1 x x 0 0 timer 0 clock = subcl out x x x 0 1 timer 0 clock = syscl out x x x 1 0 timer 0 clock = timer1 output (t1out connected internally) out x x x 1 1 timer 0 clock = t0in0 ( bp40 (1) ) in x 0 0 x x timer 1 clock = subcl x out 0 1 x x timer 1 clock = syscl x out 1 0 x x timer 1 clock = timer 0 output (t0out0 connected internally) xout 1 1 x x timer 1 clock = tim1 x in subport address (indirect write access): '7'hex of port address '9'hex bit 3bit 2bit 1 bit 0 tcip t1ip2 t1ip1 t0ip2 t0ip1 reset value: 1111b t0ip2, t0ip1 - timer 0 interrupt priority code t1ip2, t1ip1 - timer 1 interrupt priority code
35 ATAR510 4703a?4bmcu?06/03 table 15. timer/counter interrupt priority register (tcip) ) timer/counter i/o control register (tcior) table 16. timer/counter i/o control register (tcior) by using the timer/counter i/o control register (tcior) the program can configure the respective port 4 pins as either standard data i/o ports or as external signal ports for the timer 0 and buzzer. the timer 1 uses a dedicated i/o pin tim1, whose direction is controlled solely by the tccr (see figure 24). it should be noted that if a tcior bit is set low, then the corresponding port data direction register (p4ddr) bit no longer influ- ences the port direction. in the case of bp40 and bp41, the port direction is then controlled entirely by the timer/counter configuration registers (tccr,t0mo), while pins bp42 and bp43 become uni-directional buzzer outputs. code 3 2 1 0 function x x 1 1 timer 0 interrupt priority 1 x x 1 0 timer 0 interrupt priority 3 x x 0 1 timer 0 interrupt priority 5 x x 0 0 timer 0 interrupt priority 7 1 1 x x timer 1 interrupt priority 0 1 0 x x timer 1 interrupt priority 2 0 1 x x timer 1 interrupt priority 4 0 0 x x timer 1 interrupt priority 6 subport address (indirect write access): '5'hex of port address '9'hex bit 3bit 2bit 1 bit 0 tcior tcio3 tcio2 tcio1 tcio0 reset value: 1111b tcio3...0 - timer/counter i/0 mode select code 3 2 1 0 function x x x 1 bp40 - standard port mode x x x 0 bp40 - timer 0 clock input (t0in0) or timer 0 output (t0out0) x x 1 x bp41 - standard port mode x x 0 x bp41 - timer 0 gate input (t0in1) or timer 0 output (t0out1) x 1 x x bp42 - standard port mode x 0 x x bp42 - buzzer output (buz) 1 x x x bp43 - standard port mode 0 x x x bp43 - buzzer output (nbuz)
36 ATAR510 4703a?4bmcu?06/03 figure 28. timer/counter and buzzer external interface timer/counter mode register (tcmo) table 17. timer/counter mode register (tcmo) bp40 buzzer buz nbuz timer 0 t0in0 t0in1 t0out0 t0out1 timer 1 t1in t1out p4dat0 p4ddr0 bp41 p4dat1 p4ddr1 bp42 p4dat2 p4ddr2 bp43 tim1 tccr tccr tcio0 pwm,pdm melody,counter t0mo to cpu select ext. clock select ext. clock to cpu tcio1 to cpu tcio2 '0' p4dat3 p4ddr3 to cpu tcio3 '0' subport address (indirect write access): '4'hex of port address '9'hex bit 3bit 2bit 1 bit 0 tcmo t0ninv tc8 t1rst t0rst reset value: 1111b t0ninv timer 0 output (bp41) appears non-inverted at bp40 tc8 timer/counter in 8-/16-bit mode t1stp timer 1 stop/run t0stp timer 0 stop/run code 3 2 1 0 function x x x 0 timer 0 running x x x 1 timer 0 halted x x 0 x timer 1 running x x 1 x timer 1 halted x 0 x x timer/counter in 16-bit mode x 1 x x timer/counter in 8-bit mode 0 x x x inverted output bp41 appears on bp40 (bp40 = not bp41) 1 x x x non?inverted output bp41 appears on bp40 (bp40 = bp41)
37 ATAR510 4703a?4bmcu?06/03 timer/counter in 16-bit mode figure 29. 16-bit mode in 16-bit mode, timer 0 and timer 1 are cascaded thus forming a 16-bit counter (see figure 29) whereby, irrespective of the state of timer 0 interrupt mask bit (t0im), the timer 1 counts both timer 0 overflow and compares interrupt events. these are gener- ated according to the state of the timer 0 mode register as described in the t0mo table. the comparators are also cascaded so that when both timer 0 and timer 1 match their respective compare registers, timer 1 generates both an output signal and a com- pare interrupt (if unmasked). in measurement modes, only timer 0 capture register is loaded with timer 0's contents on an end-of-measurement event. timer 1 capture register operates solely as a shadow register. there is no 16-bit capture operation, so the user program must check if timer 1 has incremented between reading the lower and higher byte. likewise, there is no auto- matic suppression of spurious interrupts which could conceivably be generated between writing to timer 0 and timer 1 compare registers. timer 0 modes the timer 0 mode configuration is defined in the timer 0 mode register (t0mo). the available modes and the effect on the timer 0 interrupt and interrupt flags is shown below. in all modes except the position measurement mode, timer 0 acts as an up- counter, the related clock frequency being defined by the selected clock source and the prescaler division factor. the counter can be reset and halted at any time by the t0rst bit of the tcmo register which also resets all the interrupt status flags and capture reg- isters. whenever port 4 bp40 and bp41 pins are required for timer 0 i/o, then the appropriate tcior enable bit must be set low. in this case, the port direction switching is handled automatically by the hardware. in modes where the bp40 is not used as a timer clock input or as a melody envelope output, the bp40 outputs the same signal as that appearing on bp41. with the help of the t0ninv bit of the timer/counter mode register (tcmo), the bp41 output can be inverted so that bp40 and bp41 form a differ- ential output stage which can be used for directly driving piezo buzzers or small stepper motors. pr escal er counter counter pr escal er carry comparator compare regi ster compare register comparator overflow/compare compare interrupt to tim1 8bit/16bit mux timer 0 timer 1
38 ATAR510 4703a?4bmcu?06/03 timer 0 mode register (t0mo) table 18. timer 0 mode register (t0mo) notes: 1. the compare interrupt/status flag can only be set when counting up 2. the overflow interrupt/status flag is set on both an overflow or an underflow 3. the bp40 signals can be inverted if t0ninv=0 (tcmo register) timer 0 interrupt status register (t0sr) subport address (indirect write access): '0'hex of port address '9'hex bit 3bit 2bit 1 bit 0 t0mo t0mo3 t0mo2 t0mo1 t0mo0 reset value: 1111b t0mo3 ... 0 - timer 0 mode code code 3210 funtion assuming tcior1 = tcior0 = low interrupt set/ t0sr affected bp40 (3) bp41 cmp ofl eom 0 0 0 0 reserved -- - 0 0 0 1 reserved -- - 0 0 1 0 modulated melody mode envelope (out) tone (out) y/y y/y n/n 0 0 1 1 melody mode tone (out) tone (out) y/y y/y n/n 0 1 0 0 counter-auto reload (50% duty cycle) toggle (out)/clock (in) toggle (out) y/y y/y n/n 0 1 0 1 counter-free running (50% duty cycle) toggle (out)/clock (in) toggle (out) n/y y/y n/n 0 1 1 0 pulse density modulation pdm (out)/clock (in) pdm (out) n/y y/y n/n 0 1 1 1 pulse width modulation pwm (out)/clock (in) pwm (out) n/y y/y n/n 1 0 0 0 phase measurement signal 1 (in) signal 2 (in) n/n y/y y/y 1 0 0 1 position measurement signal 1 (in) signal 2 (in) (1) (2) n/n 1 0 1 0 low pulse width measurement clock (in) signal (in) n/y y/y y/y 1 0 1 1 high pulse width measurement clock (in) signal (in) n/y y/y y/y 1 1 0 0 counter-auto reload (strobe) strobe (out)/clock (in) strobe (out) y/y y/y n/y 1 1 0 1 counter-free running (strobe) strobe (out)/clock (in) strobe (out) n/y y/y n/y 1 1 1 0 period measurement (rising edge) clock (in) signal (in) n/y y/y y/y 1 1 1 1 period measurement (falling edge) clock (in) signal (in) n/y y/y y/y auxiliary register address (read access): ?9?hex bit 3bit 2bit 1 bit 0 t0sr not used t0eom t0ofl t0cmp reset value: x000b note: the status register is reset automatically when read and also when timer 0 is reset. t0eom timer 0 end of measurement status flag t0ofl timer 0 overflow status flag t0cmp timer 0 compare status flag
39 ATAR510 4703a?4bmcu?06/03 table 19. timer 0 interrupt status register (t0sr) the interrupt flags will be set whenever the associated condition occurs irrespective of whether the corresponding interrupt is triggered. therefore, the status flags are still set if the interrupt condition occurs when the interrupt is masked. to see exactly when the flags are set, see t0mo control code, table 17. reading from the timer/counter auxiliary register will access the timer 0 interrupt status register (t0sr). timer 0 control register (t0cr) the t0cr is responsible for the predivision of the selected timer 0 input clock (see tccr). it can be divided or used directly as a clock for the up/down counter. bit 0 is the mask bit for timer 0 interrupt. table 20. timer 0 control register (t0cr) code 3 2 1 0 function x x x 1 timer 0 compare has occurred (timer 0 = t0cp) x x 1 x timer 0 overflow or underflow has occurred x 1 x x timer 0 measurement completed subport address (indirect write access): '1'hex of port address '9'hex bit 3bit 2bit 1 bit 0 t0cr t0fs3 t0fs2 t0fs1 t0im reset value: 1111b t0fs3 ... 1 ? timer 0 prescaler division factor code t0im ? timer 0 interrupt mask code 3 2 1 0 function x x x 1 timer 0 interrupt disabled x x x 0 timer 0 interrupt enabled 0 0 0 x timer 0 prescaler divide by 256 0 0 1 x timer 0 prescaler divide by 128 0 1 0 x timer 0 prescaler divide by 64 0 1 1 x timer 0 prescaler divide by 32 1 0 0 x timer 0 prescaler divide by 16 1 0 1 x timer 0 prescaler divide by 8 1 1 0 x timer 0 prescaler divide by 4 1 1 1 x timer 0 prescaler bypassed
40 ATAR510 4703a?4bmcu?06/03 timer 0 compare register (t0cp) - byte write the compare register t0cp is 8-bit wide and must be accessed as byte wide subport (see section "addressing peripherals?). first the low nibble data is written and is then followed by the high nibble. any timer interrupts are automatically suppressed until the complete compare value has been transferred. timer 0 capture register (t0ca) - byte read note: if the timer is read (in pdm mode only) the bit order will appear reversed, so that t0ca0 = msb, t0ca1 = msb - 1 .... t0ca6 = lsb + 1, t0ca7 = lsb. the 8-bit capture register t0ca is read as byte wide subport. note, however, unlike writ- ing to the compare register, the high nibble is read first followed by the low nibble. the 8-bit timer state is captured on reading the first nibble and held until the complete byte has been read. during this transfer, the timer is free to continue counting. timer 0 free running counter modes (strobe and 50% duty cycle) in the free running counter mode, timer 0 can be used as an event counter for summing external event pulses on bp40, or as a time r with an internal time-based clock. when enabled, the counter will count up generati ng an output signal on bp41 whenever the counter contents match the compare register (see figure 30). this signal can appear either as a strobe pulse or as a simple toggling of the output state (50% duty cycle) depending on the timer mode. interrupts (if not masked) are generated every 256 clocks on the overflow condition. the current counter state can be read at any time by reading the capture register,. the compare register has no effect on the counter cycle time and will not influence interrupts. subport address (indirect read access): '9'hex of port address '9'hex bit 3bit 2bit 1bit 0 t0cp first write cycle t0cp3 t0cp2 t0cp1 t0cp0 reset value: xxxxb bit 7bit 6bit 5bit 4 second write cycle t0cp7 t0cp6 t0cp5 t0cp4 reset value: xxxxb t0cp3 ... t0cp0 - timer 0 compare register data (low nibble) - first write cycle t0cp7 ... t0cp4 - timer 0 compare register data (high nibble) - second write cycle subport address (indirect read access): '9'hex of port address '9'hex bit 7bit 6bit 5bit 4 t0ca first write cycle t0ca7 t0ca6 t0ca5 t0ca4 reset value: xxxxb bit 3bit 2bit 1bit 0 second write cycle t0ca3 t0ca2 t0ca1 t0ca0 reset value: xxxxb t0ca7. .. t0ca4 - timer 0 capture register data (high nibble) - first read cycle t0ca3 ... t0ca0 - timer 0 capture register data (low nibble) - second read cycle
41 ATAR510 4703a?4bmcu?06/03 figure 30. timer 0 free running counter mode timer 0 counter reload modes (strobe and 50% duty cycle) as in the free running mode, the counter can also be clocked from either an external sig- nal on bp40 or from an internal clock source. in this mode, the counter repetition period is completely defined by the contents of the compare register (t0cp) (see figure 31). the counter counts up with the selected clock frequency. when it reaches the value held in the compare register, the counter then returns to the zero state. at the same time, depending on the selected timer mode, the bp41 either toggles or generates a strobe pulse. if the timer 0 interrupt is unmasked, a compare interrupt is also generated. the resultant output frequency f out = fin/2 (n+1) where n = compare value (n = 1 - 255). figure 31. timer 0 counter reload mode timer clock t0out1 (bp41) overflow interrupt timer = compare register (= 4) timer resets on overflow 04 255 timer state strobe 50% duty cycle 1 2 35 6 4 1 2 35 6 0 255 255 4 1 2 35 6 0 timer clock t0out1 (bp41) compare interrupt timer = compare register (= 7) resets timer 0 7 timer state 0 50% duty cycle strobe 4 1 2 35 6 7 0 4 1 2 35 6 7 0 4 1 2 35 6
42 ATAR510 4703a?4bmcu?06/03 melody mode (with/without modulation) the non-modulated melody mode is identical to the auto-reload counter (50% duty cycle) mode. the melody tone frequency appearing on bp41 and/or bp40 is determined in exactly the same way as the value written into the comparator register. in the modu- lated melody mode, the m44c510e generates two output signals, a melody tone and an envelope pulse (see figure 32). the tone frequency output on bp41 is generated in exactly the same way as in the simple melody mode. while the envelope pulse on bp40 is a single pulse of a clock period in duration which appears shortly after loading the compare value into the compare register. in this mode, an analog switch is activated between the bp40 and bp41 outputs (see figure 33). with the external capacitor con- nected, the resultant signal on bp41 exhibits a melody chime effect with an exponential decay. figure 32. modulated melody mode figure 33. modulated melody output circuit timer clock t0out0 (bp40) compare interrupt timer = compare register resets timer 0 7 timer state 0 t0out1 (bp41) new value (=7) loaded into compare register 4 1 2 35 6 0 7 4 1 2 35 6 0 7 4 1 2 35 6 0 7 4 1 2 35 6 7 4 1 2 35 6 t0out0 t0out1 v analog switch modulated melody mode bp41 bp40 t0out0 (melody output) t0out1 (envelope) bp40 bp41 v 10...47uf r (optional) piezo buzzer v dd ss dd v ss
43 ATAR510 4703a?4bmcu?06/03 timer 0 pulse width modulation mode a pulse width modulated (pwm) signal exhibits a fixed repetition frequency and a vari- able mark space ratio. it is often used as a simple method for d/a conversion, where the high period is proportional to the digital value to be converted. therefore by connecting a simple low-pass rc network to the pwm signal, the analog value can be retrieved. timer 0 generates the pwm signal by comparing the state of the free running up counter with the contents of the compare register (see figure 34). if the result is less than the compare register value, then the bp41 output is high. if the result is greater or equal to the compare register value, then the bp41 output is set low. thus, the high phase of the pwm signal is directly propor tional to the compare register contents. a total of 256 possible discrete mark space ratios can be generated ranging from a contin- uous low signal over a variable pulse width signal to a continuous high signal. the pwm signal has a repetition period of 256 clocks, an interrupt (if unmasked) being generated on every overflow event. care should be taken if the syscl clock is used as the pwm clock source because it may stop if the cpu goes into sleep mode (see section ?power-down modes?). figure 34. timer 0 pulse width modulation pulse density modulation mode pulse density modulation (pdm) is also used for simple d/a conversion. unlike the pwm signal where the high and low signal phases are always continuous during a sin- gle repetition cycle, the pdm distributes these evenly as a series of pulses (see figure 35). this has the advantage that, if used together with an rc smoothing filter for d/a conversion, either the ripple is less than the pwm, or, for a corresponding ripple error, the filter components can be smaller or the clock frequency lower. to generate the pdm output on bp41, the pulse density is controlled by the contents of the compare register in the same way as the pwm generation. each of the pulses has a width equal to the counter clock period. timer clock t0out1 (bp41) overflow interrupt timer = compare register (= 4) 04 255 timer state t_hi t_low t_hi = (comparator value) clock period t_low = (255-comparator value) clock period 1 2 3 255 04 1 3 255 04 1 3
44 ATAR510 4703a?4bmcu?06/03 figure 35. an example 4-bit pwm/pdm comparison period measurement modes (rising and falling edge) during the period measurement mode, the counter counts the number of either internal or external clocks in one period of the bp41 input signal (see figure 36). depending the mode chosen, this will be from rising edge to the next rising edge or conversely, falling edge to the following falling edge. on the trigger edge, the counter state is loaded into the capture register and subsequently reset. the measured value remains in the cap- ture register until overwritten by the following measured value. interrupts can be generated by either an overflow condition or an end-of-measurement (eom) event. an eom event signals to the cpu that a new measured value is present in the capture reg- ister and can be read, if required. figure 36. period measurement pulse width measurement modes (high and low) in this mode, the selected clock source is gated to the counter for the duration of each input pulse received on bp41 (see figure 37). whether the measurement takes place during the high or low phase depends on the selected mode. at the end of each pulse, the counter state is loaded into the capture register and subsequently reset. interrupts can be generated by either an overflow condition or an end-of-measurement (eom) event. an eom event signals the cpu that a new measured value is present in the cap- ture register and can be read if required. pwm=0.25 pdm=0.25 pwm=0.75 pdm=0.75 repetition period t0in1 (bp41) t_period eom interrupt captures and resets timer falling edge triggered t_period rising edge triggered
45 ATAR510 4703a?4bmcu?06/03 figure 37. pulse width measurement phase measurement mode this mode allows the timer 0 to measure the phase misalignment between two 1:1 mark space ratio input signals connected to the bp40 and bp41 pins (see figure 38). the counter clock is gated with the phase misalignment period (tp), during which time the counter increments with the selected clock frequency. this misalignment period is defined as the period during which bp40 is high and bp41 is low. capturing and reset- ting of the counter always takes place on the rising edge of bp41. the measured value remains in the capture register until overwritten by the next measurement. interrupts can be generated by either an overflow condi tion or an end-of-measurement (eom) event. an eom event signals to the cpu that a new measured value is present in the capture register and can be read, if required. figure 38. phase measurement position measurement mode this mode is intended for the evaluation of positional sensors with bi-phase output sig- nals. figure 39 illustrates a typical positional sensor system which delivers both incremental positional stepping signals and also directional information. the direction can be deduced from the relative phase of the two signals. therefore if bp40 is high on the rising edge of bp41, the moving mask travels to the left and if it is low then it travels to the right. the direction (left/right) information is used to set the direction of the up/down counter which enables the bp40 pulses to be counted. assuming that the sys- tem has been reset on a reference position, the counter will always hold the absolute current position of the moving mask. this can be read by the cpu if necessary. this mode is the only one in which the counter is allowed to decrement. therefore, in this case it is possible for both an underflow or an overflow to occur. the overflow interrupt (if unmasked) will trigger on either of these conditions while the compare interrupt on the other hand will only trigger if the counter is counting upwards. to differentiate between an overflow or underflow, the compare value can be set to '0' hex, for example. an over- flow would then set both the overflow and compare status flags while an underflow sets the overflow status flag only. t0in1 (bp41) t_low t_high eom interrupt captures and resets timer t0in1 (bp41) t0in0 (bp40) eom interrupt tp tp tp captures and resets timer
46 ATAR510 4703a?4bmcu?06/03 figure 39. position measurement mode timer 1 modes timer 1 is meant to perform event counting and timing functions (see figure 27). it has, unlike the timer 0, no gated clock or externally triggered capture modes. the counter counts up with an internal or external clock, depending on the state of the timer 1 con- trol register (t1cr) and the timer/counter clock control register (tccr) and generates a compare interrupt whenever the counter matches timer 1 compare regis- ter. this is the only timer 1 interrupt source. masking can be performed using the mask bit in the timer 1 control register (t1cr) and priority can be defined in the timer/counter interrupt priority register (tcip). the tim1 pin is used by the timer 1 either as clock/event input or timer output. i/o control of the timer 1 pin tim1 is con- trolled entirely by the hardware, therefore if the tim1 is selected as an external clock or event source (in the tccr), there can be no timer 1 signal output. in this case, the timer would be used solely to generate interrupts. in autostop operation, the timer 1 will halt both itself and timer 0 whenever the timer 1 compare value is reached. this feature c an be used for example to generate an exact burst of pulses. both timers will remain stopped until restarted. restarting is performed in the normal way by setting the appropriate control bits in the timer/counter mode register (tcm0). t0in1 (bp41) t0in0 (bp40) typical sensor light light static mask moving mask t0in0 t0in1 left movement right movement timer n n+1 n+2 n+3 n n-1 n-2 n-3
47 ATAR510 4703a?4bmcu?06/03 timer 1 mode register (t1mo) table 21. timer 1 mode register (t1mo) timer 1 control register (t1cr) the t1cr is responsible for the predivision of the selected timer 1 input clock (see tccr). it can be divided or used directly as clock for the up counter. bit 0 is the mask bit for the timer 1 interrupt. table 22. timer 1 control register (t1cr) subport address (indirect write access): '2'hex of port address '9'hex bit 3bit 2bit 1 bit 0 t1mo t1mo3 t1mo2 t1mo1 t1mo0 reset value: 1111b t1mo3 ... 0 - timer 1 mode code code 3 2 1 0 function compare interrupt x x 0 0 counter free running (50% duty cycle) yes x x 0 1 counter auto reload (50% duty cycle) yes x x 1 0 pulse width modulation yes x x 1 1 counter auto-reload (strobe output) yes x 0 x x increment on falling edge of clock ? x 1 x x increment on rising edge of clock ? 1 x x x normal operation (no autostop) yes 0 x x x autostop operation (timer 1 stops timer 2) yes subport address (indirect write access): '3'hex of port address '9'hex bit 3bit 2bit 1 bit 0 t1cr t1fs3 t1fs2 t1fs1 t1im reset value: 1111b t1fs3 ... 1 - timer 1 prescaler division factor code t1im - timer 1 interrupt mask code 3 2 1 0 function x x x 1 timer 1 interrupt disabled x x x 0 timer 1 interrupt enabled 0 0 0 x timer 1 prescaler divide by 256 0 0 1 x timer 1 prescaler divide by 128 0 1 0 x timer 1 prescaler divide by 64 0 1 1 x timer 1 prescaler divide by 32 1 0 0 x timer 1 prescaler divide by 16 1 0 1 x timer 1 prescaler divide by 8 1 1 0 x timer 1 prescaler divide by 4 1 1 1 x timer 1 prescaler bypassed
48 ATAR510 4703a?4bmcu?06/03 timer 1 compare register (t1cp) - byte write the compare register t1cp is 8 bits wide and must be accessed as a byte wide subport (see section "addressing peripherals"). the data is written low nibble first, followed by the high nibble. any timer interrupts are automatically suppressed until the complete compare value has been transferred. timer 1 capture register (t1ca) - byte read the 8-bit capture register t1ca is read as byte wide subport. note, however, unlike the writing to the compare register, the high nibble is read first followed by low nibble. the 8-bit timer state is captured on reading the first nibble and held until the complete byte has been read. during this transfer, the timer is free to continue counting. the previous capture value will be held until the timer is restarted again. timer 1 counter free running (50% duty cycle) in the free running counter mode, the counter counts up with either an internal or exter- nal clock and cycles through all 256 timer states. on the clock following a match between the compare register (t1cr) and the counter, a compare interrupt (if unmasked) is generated and the tim1 pin is toggled (see figure 40). subport address (indirect read access): '8'hex of port address '9'hex bit 3 bit 2 bit 1 bit 0 t1cp first write cycle t1cp3 t1cp2 t1cp1 t1cp0 reset value: xxxxb bit 7 bit 6 bit 5 bit 4 second write cycle t1cp7 t1cp6 t1cp5 t1cp4 reset value: xxxxb t1cp3 ... t1cp0 - timer 1 compare register data (low nibble) - first write cycle t1cp7 ... t1cp4 - timer 1 compare register data (high nibble) - second write cycle subport address (indirect read access): '8'hex of port address '9'hex bit 7 bit 6 bit 5 bit 4 t1ca first write cycle t1ca7 t1ca6 t1ca5 t1ca4 reset value: xxxxb bit 3 bit 2 bit 1 bit 0 second write cycle t1ca3 t1ca2 t1ca1 t1ca0 reset value: xxxxb t1ca7. .. t1ca4 - timer 1 capture register data (high nibble) - first read cycle t1ca3 ... t1ca0 - timer 1 capture register data (low nibble) - second read cycle
49 ATAR510 4703a?4bmcu?06/03 figure 40. timer 1 counter free running (50% duty cycle) timer 1 counter auto reload (strobe and 50% duty cycle) in the auto-reload mode, the counter counts up with either an internal or external clock. on the clock cycle following a match between the compare register (t1cr) and the counter, a compare interrupt (if unmasked) is generated. the tim1 output is either strobed or toggled and the counter reset (see figure 41). therefore, the counter cycle period is defined by the contents of the co mpare register. in 50% duty cycle mode the frequency of tim1 is: f tim1 = f in /2(n+1) where the compare value (n) =1 ... 255 figure 41. timer 1 counter auto reload timer 1 pulse width modulation the timer 1 generates the pwm signal by comparing the state of the free running up counter with the contents of the compare register (see figure 42). if the result is less or equal to the compare register value, then the tim1 output is high. if the result is greater than the compare register value, then the tim1 output is set low. thus, the high phase of the pwm signal is directly proportional to the compare register contents. a total of 256 possible discrete mark space ratios can be generated ranging from a continuous low signal over a variable pulse width signal. the pwm signal has a repetition period of 256 clock periods, an interrupt (if unmasked) being generated on every compare event. timer clock t1out (tim1) compare interrupt timer = compare register (= 4) 04 255 timer state 1 2 35 6 4 1 2 35 6 0 255 255 4 1 2 35 6 0 (clock set to rising edge) 50% duty cycle timer clock t1out (tim1) compare interrupt timer = compare register (= 7) resets timer 0 7 timer state 0 50% duty cycle strobe 4 1 2 35 6 7 0 4 1 2 35 6 7 0 4 1 2 35 6 (clock set to neg. edge)
50 ATAR510 4703a?4bmcu?06/03 care should be taken if syscl is used as the pwm clock source. the pwm output may stop if the cpu goes into sleep made depending on the programming of the nstop bit in the cm-register. if using this mode of operation it is recommended to set the bit nstop =1. figure 42. timer 1 pulse width modulation buzzer module the buzzer is a 4 stage frequency divider which divides the subcl and depending on the state of the buzzer control register (bzcr) can output one of four frequencies. an external piezo or buzzer can be driven by the complementary buzzer outputs (buz and nbuz) which are directed to port 4 (bp42 and bp43) under control of the timer/counter i/o register (tcior) as shown in figure 28. when the buzzer is switched off, both of the buzzer outputs take up the same logical state. this is controlled by the bzop bit of the bzcr. figure 43. buzzer module timer clock t1out (tim1) timer = compare register (=4) 04 255 timer state compare interrupt t_hi t_low t_hi = (comparator value) clock period t_low = (256-comparator value) clock period 1 2 3 255 04 1 3 255 04 1 3 2 2 subcl ck bzcr bzof bzfs2 bzop r 4 stage divider subcl (32 khz) subcl/4 (8 khz) subcl/8 (4 khz) subcl/16 (2 khz) bzfs1 r r r buz nbuz 4:1 mux
51 ATAR510 4703a?4bmcu?06/03 buzzer control register (bzcr) table 23. buzzer control register (bzcr) figure 44. buzzer waveform subport address (indirect write access): 'a'hex of port address '9'hex bit 3 bit 2 bit 1 bit 0 bzcr bzfs2 bzfs1 bzop bzof reset value: 1111b bzfs2,bzfs2 - buzzer frequency select code bzop - buzzer output stop state bzof - buzzer off/on code 3 2 1 0 function x x x 0 buzzer on x x x 1 buzzer off x x 0 x buzzer output stop state: bp42 = bp43 = low x x 1 x buzzer output stop state: bp42 = bp43 = high 0 0 x x buzzer frequency: 32 khz (= subcl) 0 1 x x buzzer frequency: 8 khz (= subcl/4) 1 0 x x buzzer frequency: 4 khz (= subcl/8) 1 1 x x buzzer frequency: 2 khz (= subcl/16) buz nbuz buz nbuz buzzer off bzop=1 bzop=0
52 ATAR510 4703a?4bmcu?06/03 emulation figure 45. emulation all marc4 controllers have a special emulation mode. it is activated by setting the te pin to logic high level after reset. in this mode, the internal cpu core is inactive and the i/o bus is available via port 0 and port 1 to allow the emulator the access to the on-chip peripherals. the emulator contains a special emulation cpu with a marc4 core and additional breakpoint logic and takes over the core function. the basic function of the emulator is to evaluate the customer's program and hardware in real-time. mtp support the atam510 (t48c510) from atmel provides full pin compatible multi-time program- mable (mtp) support for the ATAR510. this device is equipped with eeprom memory and allows in-system testing and real-time execution of up to 4-kbyte application pro- grams along with nonvolatile configuration of the ATAR510 mask option settings. for further details please refer to the atam510 (t48c510) datasheet. noise considerations when designing the microcontroller based application, several factors should be taken into consideration to increase noise i mmunity and reduce electromagnetic emission (eme). many such potential problems can be avoided by careful layout of the printed cir- cuit board (pcb). the pcb contains many parasitic components which at first sight are not apparent. pcb tracks can act as antennas or as coupling capacitors. long stretches of parallel tracks and long high frequency signal lines should thus be avoided wherever possible to minimize the chance of picking up or transmitting unwanted signals. noise immunity the following guidelines will increase system noise immunity: unconnected inputs should not be left open. if port pins are not required then it is recommended to set pull-up or pull-down options on these pins. special care should be taken when laying out the pcb that interrupt, reset and clock signal lines are kept short and are carefully shielded or have sufficient spacing from other on board noise generating sources. a quartz crystal should always be located right next to the microcontroller crystal oscillator terminals (oscin and oscout), the connections being always very short. this avoids, not only signal coupling onto the clock source, but can also reduces eme. core target chip ev c eprom core tcl clock tcl reset nrst mode te nrst tcl data address i/o-controlbus i/o-bus application p o r t 1 p o r t 0 port 1 port 0 nrst
53 ATAR510 4703a?4bmcu?06/03 pcb's should, where economically possible, be equipped with adequate ground planes. the microcontroller power supply should be decoupled with an electrolytic capacitance (approximate 10 f) in parallel with a ceramic capacitance (approximate 100 nf) situated as close to the microcontroller device as possible. electromagnetic emissions electromagnetic emmisions are caused by rapidly changing electrical currents (di/dt) in long antenna like connection lines and cables. this can result in electrical interference on other telecommunication devices. these current spikes are more often than not present in the system power supply lines and driver signal lines. the following guide will help to reduce eme: keep the length of pcb current switching signal tracks to a minimum.. adopt a pcb star power routing system connected at one point. many of the microcontroller port outputs can be configured with several drive strengths. this means that a high drive output will switch a signal faster than for example a standard drive output. the resulting change in current in the signal and power lines will also increase, causing an increase in eme. so wherever speed and drive current is not necessary the ports should be configured with the lowest drive possible. if possible, write the application program to avoid multiple outputs switching at any instant. cables can be equipped with ferrite rings to slow current spikes or the system can be encased in a grounded conducting casing. note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at any condition above those indicated in the operational section of these specification is not implied. exposure to absolute maximum rating conditions for an extended period may affect device reliability. all inputs and outputs are protected against high electrostatic voltages (4kv, hbm) or electric fields. however, p recau- tions to minimize the build-up of electrostatic charges during handling are recommended. reliability of operation is enhanced i f unused inputs are connected to an appropriate logic voltage level (e.g., v dd ). absolute maximum ratings voltages are given to v ss parameters symbol value unit supply voltage v dd -0.3 to +7 v input voltage (on any pin) v in v ss -0.3 v in v dd +0.3 v output short circuit duration t short indefinite s operating temperature range t amb -40 to +85 c storage temperature range t stg -65 to +150 c thermal resistance (sso44) r thja 110 k/w soldering temperature (t 10 s) t sld 260 c
54 ATAR510 4703a?4bmcu?06/03 dc operating characteristics supply voltage v dd = 5 v, v ss = 0 v, t amb = -40 to 85c unless otherwise specified. typical values relate to v dd = 5 v, t amb = 25c and are for reference only. parameters test conditions symbol min. typ. max. unit power supply supply voltage v dd 2.2 6.2 v active current cpu running testrom at syscl_irc3 i dd 200 500 a quotient i dd /syscl_ir3 cpu running testrom at syscl_irc3 i ddq 0.25 0.5 a/khz halt current cpu in sleep mode, nstop = 0 i halt 0.1 0.5 a power-on reset threshold voltage por threshold voltage v por 0.8 1.0 1.5 v schmitt trigger input voltage: (all inputs except port 5, 7 and c) negative-going threshold voltage v dd = 2.4 to 6.2 v v t- v ss 0.4 v dd v positive-going threshold voltage v dd = 2.4 to 6.2 v v t+ 0.55 v dd v dd v hysteresis (vt+ - vt-) v dd = 2.4 to 6.2 v v h 0.1 v dd input pins: nrst and te input voltage low v dd = 2.4 to 6.2 v v il v ss 0.2 v dd v input voltage high v dd = 2.4 to 6.2 v v ih 0.8 v dd v dd v input nrst with pull-up resistor input low current v dd = 2.4 v, v il = v ss v dd = 5.0 v i il -1.0 -5 -1.5 -10 -3.0 -18 a a input te with pull-down resistor input high current v dd = 5.0 v i ih 11.42ma all bi-directional ports and tim1 input voltage low v dd = 2.4 to 6.2 v v il v ss 0.2 v dd v input voltage high v dd = 2.4 to 6.2 v v ih 0.8 v dd v dd v dynamic input low current (pull-up) v dd = 2.4 v, v il = v ss v dd = 5.0 v i il -1.0 -5 -1.5 -10 -3.0 -18 a a dynamic input high current (pull-down) v dd = 2.4 v, v ih = v dd v dd = 5.0 v i ih 1.0 5 1.5 10 2.5 18 a a output low current standard/low drive v dd = 2.4 v v ol = 0.2 v dd v dd = 5.0 v i ol 1 6 2 9 4 13 ma ma note: the total sum of all port static output currents must not exceed 100 ma. the sum of all port currents switched at any instant (di/dt) must not exceed 30 ma.
55 ATAR510 4703a?4bmcu?06/03 output low current high drive v dd = 2.4 v v ol = 0.2 v dd v dd = 5.0 v i ol 2 12 4 18 7 30 ma ma output high current low drive v dd = 2.4 v v oh = 0.8 v dd v dd = 5.0 v i oh -0.3 -2.0 -0.5 -2.5 -1.5 -3.3 ma ma output high current standard drive v dd = 2.4 v v oh = 0.8 v dd v dd = 5.0 v i oh -1 -6 -2 -8 -4 -13 ma ma output high current high drive v dd = 2.4 v v oh = 0.8 v dd v dd = 5.0 v i oh -2 -12 -4 -15 -8 -30 ma ma bi-directional port bp4, bp5, bp7, bpa, bpb and bpc input low current static pull-up (30 k ) v dd = 2.4 v v dd = 5.0 v i il i il -15 -100 -25 -150 -45 -220 a a input high current static pull-down (30 k ) v dd = 2.4 v v dd = 5.0 v i ih i ih 15 100 25 150 45 220 a a input low current static pull-up (4 k ) v dd = 2.4 v v dd = 5.0 v i il i il -0.2 -1 -0.3 -1.35 -0.5 -2 ma ma input high current static pull-down (4 k ) v dd = 2.4 v, v il = v ss v dd = 5.0 v i ih i ih 0.15 1 0.25 1.4 0.5 2 ma ma dc operating characteristics (continued) supply voltage v dd = 5 v, v ss = 0 v, t amb = -40 to 85c unless otherwise specified. typical values relate to v dd = 5 v, t amb = 25c and are for reference only. parameters test conditions symbol min. typ. max. unit note: the total sum of all port static output currents must not exceed 100 ma. the sum of all port currents switched at any instant (di/dt) must not exceed 30 ma. ac characteristics supply voltage v dd = 2.4 to 6.2 v, v ss = 0 v, t amb = -40 to 85c unless otherwise specified. typical values relate to v dd = 5 v, t amb = 25c and are for reference only. parameters test conditions symbol min. typ. max. unit reset timing power-on reset delay v dd u v por t por 80 ms nrst input low time t nrst 4s interrupt request input timing int. request low time t irl 50 ns int. request high time t irh 50 ns internal rc oscillator (for additional characteristics see figure 53 to figure 55 standby current of irc0 cpu in sleep mode, sc = 0011b, cm = 1100b i irc0 300 500 a syscl_irc0 cpu active, sc = 0011b, cm = 1100b f syscl 3.5 7.0 10.5 mhz standby current of irc1 cpu in sleep mode, sc = 0111b, cm = 1101b i irc1 150 250 a note: 1. customer mask option (not subject to production test)
56 ATAR510 4703a?4bmcu?06/03 syscl_irc1 cpu active, sc = 0111b, cm = 1101b f syscl 1.9 3.0 4.5 mhz standby current of irc2 cpu in sleep mode, sc = 1011b, cm = 1110b i irc2 100 150 a syscl_irc2 cpu active, sc = 1011b, cm = 1110b f syscl 1.4 2.0 3.0 mhz standby current of irc3 cpu in sleep mode, sc = 1111b, cm = 1111b i irc3 40 70 a syscl_irc3 cpu active, sc = 1111b, cm = 1111b f syscl 0.60 0.80 1.3 mhz stability v dd = 5 v 20 % df/f 0 5 % system clock crystal/ceramic oscillator (for additional characteristics see figure 47) standby current cpu in sleep mode, 4-mhz crystal active i xtal 125 a start-up time v dd = 2.4 v t startup 810ms stability v dd = 3 v to 5.5 v df/f 0 0.3 0.5 ppm rc oscillator - external resistor (for additional characteristics see figure 50 to figure 52) standby current cpu in sleep mode, r ext = 150 k (1 %) i xrc 125 a frequency cpu active, r ext = 150 k f syscl 1.8 2.0 2.2 mhz stability v dd = 2.4 v to 5.5 v df/f 0 10 % 32-khz crystal oscillator active current cpu active/running i dd32k 10 a halt current cpu in sleep mode i haltx 1.0 1.5 a start-up time v dd = 2.4 v t startup 1.5 s stability av dd = 100 mv df/f 0 0.1 0.3 ppm integrated input/output capacitances (1) c in c out 20 20 pf pf external clock input at sclin, tim1 and t0in sclin input clock f sclin = 2 f syscl cpu active, v dd > 2.4 v rise/fall time < 50 ns, see figure 47 f syscl 48mhz tim1, t0in input frequency rise/fall time < 30 ns f in 10 mhz ac characteristics (continued) supply voltage v dd = 2.4 to 6.2 v, v ss = 0 v, t amb = -40 to 85c unless otherwise specified. typical values relate to v dd = 5 v, t amb = 25c and are for reference only. parameters test conditions symbol min. typ. max. unit note: 1. customer mask option (not subject to production test)
57 ATAR510 4703a?4bmcu?06/03 figure 46. crystal equivalent circuit figure 47. worst case minimum/maximum system frequency (using external rc or crystal oscillator) crystal characteristics parameters test conditions symbol min. typ. max. unit 32-khz crystal crystal frequency f x 32.768 khz series resistance rs 30 50 k static capacitance c0 1.5 pf dynamic capacitance c1 3 ff load capacitance c l 81012.5pf system clock crystal crystal frequency f x 1.5 4 8 mhz series resistance rs 30 50 static capacitance c0 2 4.5 pf dynamic capacitance c1 3 15 ff l c1 rs c0 oscin oscout equivalent circuit 0.001 0.010 0.100 1.000 10.000 100.000 01234567 v dd (v) f syscl (mhz) f sysclmax f sysclmin
58 ATAR510 4703a?4bmcu?06/03 figure 48. i dd = f (f syscl ), v dd = 3 v figure 49. i dd = f (f syscl ), v dd = 5 v figure 50. f syscl = f (t amb ); external rc 0.01 0.10 1.00 10.00 100.00 1000.00 10000.00 10 100 1000 10000 f syscl (khz) i dd ( a) v dd = 3 v t amb = 25c 100% active standby halt 0.01 0.10 1.00 10.00 100.00 1000.00 10000.00 10 100 1000 10000 i dd ( a) v dd = 5 v t amb = 25c f syscl (khz) 100% active standby halt 1900 1950 2000 2050 2100 2150 2200 -40 -20 0 20 40 60 80 100 t amb (c) f syscl (khz) v dd = 3 v v dd = 5 v r ext = 150 k
59 ATAR510 4703a?4bmcu?06/03 figure 51. f syscl = f (r ext ) figure 52. f syscl = f (v dd , r ext ) figure 53. f syscl = f (v dd ); internal rc 100 1000 10000 10 100 1000 r ext (k ) f syscl (khz) v dd = 5 v t amb = 25c 0 1000 2000 3000 4000 5000 6000 1.5 2.5 3.5 4.5 5.5 6.5 v dd (v) f syscl (khz) r ext = 477 k r ext = 150 k r ext = 47k t amb = 25c 0 1000 2000 3000 4000 5000 6000 7000 1.5 2.5 3.5 4.5 5.5 6.5 v dd (v) f syscl (khz) t amb = 25c f irc3 f irc2 f irc1 f irc0
60 ATAR510 4703a?4bmcu?06/03 figure 54. f syscl = f (t amb ), v dd = 3 v figure 55. f syscl = f (t amb ), v dd = 5 v figure 56. typical high output driver, v dd = 3 v 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 -40 -20 0 20 40 60 80 100 f syscl (khz) v dd = 3 v f irc3 f irc2 f irc1 f irc0 t amb (c) 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 -40 -20 0 20 40 60 80 100 t amb (c) f syscl (khz) f irc0 f irc1 f irc2 f irc3 v dd = 5 v -12 -10 -8 -6 -4 -2 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 v dd - v oh (v) i oh (ma) high drive standard drive low drive v dd = 3 v
61 ATAR510 4703a?4bmcu?06/03 figure 57. typical low output driver, v dd = 3 v figure 58. typical low output driver, v dd = 5 v figure 59. typical high output driver pad layout, v dd = 5 v 0 2 4 6 8 10 12 14 0.0 0.5 1.0 1.5 2.0 2.5 3.0 v ol (v) i ol (ma) high drive standard/low drive v dd = 3 v 0 5 10 15 20 25 30 35 012345 v ol (v) i ol (ma) high drive standard/low drive v dd = 5 v -35 -30 -25 -20 -15 -10 -5 0 012345 v dd - v oh (v) i oh (ma) high drive standard drive low drive v dd = 5 v
62 ATAR510 4703a?4bmcu?06/03 pad layout figure 60. pad assignments 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 23 24 bp40 bp00 bp01 bp02 bp03 bpa0 sclin vss oscin oscout vdd bp73 25 26 27 28 bp70 bp71 bp72 te nrst bpb0 bpb1 bpb2 bpb3 bp41 ATAR510 bp43 bp42 29 30 31 34 35 36 37 38 39 40 41 bpa1 bpa2 bpa3 bp10 bp11 bp12 bp13 tim1 bp53 bp50 bp51 bp52 avdd vss bp61 bp60 22 bpc0 bpc1 32 33 42 43 die size: 2.26 x 2.59 mm pad size: 100 x 100 m thickness: 480 25 m ( 19 1 mil) bpc2 bpc3 44 mask/ chip id
63 ATAR510 4703a?4bmcu?06/03 table 24. pad coordinates pad number name x-coord y-coord 1 sclin 113.8 350.55 2 bp61 113.8 500.55 3 bp60 113.8 650.55 4 bpb3 113.8 800.55 5 bpb2 113.8 950.55 6 bpb1 113.8 1100.55 7 bpb0 113.8 1250.55 8 bpc3 113.8 1400.55 9 bpc2 113.8 1550.55 10 avdd 113.8 1700.55 11 oscin 113.8 1850.55 12 oscout 501.8 1950.20 13 nrst 651.8 1950.20 14 bpa0 801.8 1950.20 15 bpa1 951.8 1950.20 16 bpa2 1101.8 1950.20 17 bpa3 1251.8 1950.20 18 bp10 1401.8 1950.20 19 bp11 1551.8 1950.20 20 bp12 1701.8 1950.20 21 bp13 1851.8 1950.20 22 bpc0 2001.8 1950.20 23 te 2151.8 1950.20 24 bpc1 2219.7 1646.10 25 tim1 2219.7 1496.10 26 bp00 2219.7 1346.10 27 bp01 2219.7 1196.10 28 bp02 2219.7 1046.10 29 bp03 2219.7 896.10 30 bp40 2219.7 746.10 31 bp41 2219.7 596.10 32 bp42 2219.7 446.10 33 bp43 2219.7 296.10 34 vdd 2219.7 146.10 35 bp50 1910.3 144.65 36 bp51 1760.3 144.65 37 bp52 1610.3 144.65 38 bp53 1460.3 144.65 39 vss 1160.3 144.65 40 bp70 1010.3 144.65 41 bp71 860.3 144.65 42 bp72 710.3 144.65 43 bp73 560.3 144.65 44 vss 410.3 144.65
64 ATAR510 4703a?4bmcu?06/03 figure 61. pin connections sso44-package 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 s c l i n b p c 0 b p 0 0 b p 1 2 b p 1 1 b p 1 0 o s c i n o s c o u t b p 0 1 b p 0 2 b p 0 3 n r s t v s s v d d b p 4 3 b p 4 2 b p 4 1 b p 4 0 b p b 3 b p b 2 b p b 1 b p b 0 b p 7 0 b p 7 1 b p 7 2 b p 7 3 b p 5 3 b p 5 2 b p 5 1 b p 5 0 t i m 1 b p a 3 b p a 2 b p a 1 b p a 0 t e a v d d b p 6 1 [ i n t y ] b p 6 0 [ i n t x ] ATAR510 2 1 2 2 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 3 2 4 4 1 4 2 4 3 4 4 b p c 1 b p 1 3 v s s b p c 3 b p c 2 technical drawings according to din specifications package sso44 dimensions in mm 0.25 0.10 0.3 0.8 18.05 17.80 16.8 2.35 9.15 8.65 7.50 7.30 10.50 10.20 0.25 44 23 1 22
65 ATAR510 4703a?4bmcu?06/03 application examples figure 62. ATAR510 as keyboard controller figure 63. driving a lcd panel with 1/3 duty ATAR510 port a port b port 1 port 4 port 5 port 7 sclin bp02 bp01 bp00 8 16 pc keyboard matrix v v v dd cc ss bp60 bp61 + 5 v data clock gnd shield pc connector + 5 v lock shift num 3 led 68 k (1%) nrst 22 nf optional 100 nf port c port a port b port 5 sclin bp73 (power save) bp72 bp70 bp71 com0 com1 com2 100 nf v dd gnd 3 470 k 1 % precision resistor ATAR510 v dd v ss v dd 3 470 k
66 ATAR510 4703a?4bmcu?06/03 ordering information please select the option settings from the list below and insert rom crc. output input output input port 0 port 5 bp00 [ ] cmos [ ] switched pull-up bp50 [ ] cmos [ ] switched pull-up [ ] switched pull-down [ ] open drain [n] [ ] switched pull-down bp01 [ ] cmos [ ] switched pull-up [ ] open drain [p] [ ] static pull-up [ ] switched pull-down [ ] static pull-down bp02 [ ] cmos [ ] switched pull-up bp51 [ ] cmos [ ] switched pull-up [ ] switched pull-down [ ] open drain [n] [ ] switched pull-down bp03 [ ] cmos [ ] switched pull-up [ ] open drain [p] [ ] static pull-up [ ] switched pull-down [ ] static pull-down port 1 bp52 [ ] cmos [ ] switched pull-up bp10 [ ] cmos [ ] switched pull-up [ ] open drain [n] [ ] switched pull-down [ ] open drain [n] [ ] switched pull-down [ ] open drain [p] [ ] static pull-up [ ] open drain [p] [ ] static pull-up [ ] static pull-down [ ] static pull-down bp53 [ ] cmos [ ] switched pull-up bp11 [ ] cmos [ ] switched pull-up [ ] open drain [n] [ ] switched pull-down [ ] open drain [n] [ ] switched pull-down [ ] open drain [p] [ ] static pull-up [ ] open drain [p] [ ] static pull-up [ ] static pull-down [ ] static pull-down port 6 bp12 [ ] cmos [ ] switched pull-up bp60 [ ] cmos [ ] switched pull-up [ ] open drain [n] [ ] switched pull-down [ ] open drain [n] [ ] switched pull-down [ ] open drain [p] [ ] static pull-up [ ] open drain [p] [ ] static pull-up []static pull-down []static pull-down bp13 [ ] cmos [ ] switched pull-up bp61 [ ] cmos [ ] switched pull-up [ ] open drain [n] [ ] switched pull-down [ ] open drain [n] [ ] switched pull-down [ ] open drain [p] [ ] static pull-up [ ] open drain [p] [ ] static pull-up []static pull-down []static pull-down port 4 port 7 bp40 [ ] cmos [ ] switched pull-up bp70 [ ] cmos [ ] switched pull-up [ ] open drain [n] [ ] switched pull-down [ ] open drain [n] [ ] switched pull-down [ ] open drain [p] [ ] static pull-up [ ] open drain [p] [ ] static pull-up []static pull-down []static pull-down bp41 [ ] cmos [ ] switched pull-up bp71 [ ] cmos [ ] switched pull-up [ ] open drain [n] [ ] switched pull-down [ ] open drain [n] [ ] switched pull-down [ ] open drain [p] [ ] static pull-up [ ] open drain [p] [ ] static pull-up []static pull-down []static pull-down bp42 [ ] cmos [ ] switched pull-up bp72 [ ] cmos [ ] switched pull-up [ ] open drain [n] [ ] switched pull-down [ ] open drain [n] [ ] switched pull-down [ ] open drain [p] [ ] static pull-up [ ] open drain [p] [ ] static pull-up []static pull-down []static pull-down bp43 [ ] cmos [ ] switched pull-up bp73 [ ] cmos [ ] switched pull-up [ ] open drain [n] [ ] switched pull-down [ ] open drain [n] [ ] switched pull-down [ ] open drain [p] [ ] static pull-up [ ] open drain [p] [ ] static pull-up []static pull-down []static pull-down
67 ATAR510 4703a?4bmcu?06/03 file: _____________________ . hex crc: ____________________ . hex aproval date: _________________ signature: _________________________ port a port c bpa0 [ ] cmos [ ] switched pull-up bpc0 [ ] cmos [ ] switched pull-up [ ] open drain [n] [ ] switched pull-down [ ] open drain [n] [ ] switched pull-down [ ] open drain [p] [ ] static pull-up [ ] open drain [p] [ ] static pull-up []static pull-down []static pull-down bpa1 [ ] cmos [ ] switched pull-up bpc1 [ ] cmos [ ] switched pull-up [ ] open drain [n] [ ] switched pull-down [ ] open drain [n] [ ] switched pull-down [ ] open drain [p] [ ] static pull-up [ ] open drain [p] [ ] static pull-up []static pull-down []static pull-down bpa2 [ ] cmos [ ] switched pull-up bpc2 [ ] cmos [ ] switched pull-up [ ] open drain [n] [ ] switched pull-down [ ] open drain [n] [ ] switched pull-down [ ] open drain [p] [ ] static pull-up [ ] open drain [p] [ ] static pull-up []static pull-down []static pull-down bpa3 [ ] cmos [ ] switched pull-up bpc3 [ ] cmos [ ] switched pull-up [ ] open drain [n] [ ] switched pull-down [ ] open drain [n] [ ] switched pull-down [ ] open drain [p] [ ] static pull-up [ ] open drain [p] [ ] static pull-up []static pull-down []static pull-down port b bpa-reset []no bpb0 [ ] cmos [ ] switched pull-up [ ] bpa0 and bpa1 = low [ ] open drain [n] [ ] switched pull-down [ ] bpa0 and bpa1 and bpa2 = low [ ] open drain [p] [ ] static pull-up [ ] bpa0 and bpa1 and bpa2 and bpa3 = low [ ] static pull-down [ ] bpa0 and bpa1 = high bpb1 [ ] cmos [ ] switched pull-up [ ] bpa0 and bpa1 and bpa2 = high [ ] open drain [n] [ ] switched pull-down [ ] bbpa0 and bpa1 and bpa2 and bpa3 = high [ ] open drain [p] [ ] static pull-up watchdog []0.5 s []disabled []static pull-down []1 s bpb2[]cmos []switched pull-up []2 s [ ] open drain [n] [ ] switched pull-down oscin [ ] no integrated capactance [ ] open drain [p] [ ] static pull-up [ ] internal cap (_pf) [ ] static pull-down oscout [ ] no integrated capactance bpb3 [ ] cmos [ ] switched pull-up [ ] internal cap (_pf) [ ] open drain [n] [ ] switched pull-down package []dit [ ] open drain [p] [ ] static pull-up [ ] dow []static pull-down []sso44 tim1 bpb0 [ ] cmos [ ] switched pull-up [ ] open drain [n] [ ] switched pull-down [ ] open drain [p] [ ] static pull-up [ ] static pull-down ordering information please select the option settings from the list below and insert rom crc. output input output input
68 ATAR510 4703a?4bmcu?06/03 table of contents features ................................................................................................. 1 description ............................................................................................ 1 pin configuration .................................................................................. 2 pin description ..................................................................................... 2 marc4 architecture general description .......................................... 4 components of marc4 core ...............................................................................4 interrupt structure .................................................................................................8 master reset ......................................................................................................11 clock generation ................................................................................................12 clock management .............................................................................................16 peripheral modules ............................................................................. 18 addressing peripherals .......................................................................................18 bi-directional ports ..............................................................................................21 interval timers/prescaler ....................................................................................29 watchdog timer .................................................................................................32 timer/counter module (tcm) .............................................................................32 buzzer module ....................................................................................................50 emulation ............................................................................................................52 mtp support .......................................................................................................52 noise considerations ..........................................................................................52 absolute maximum ratings ............................................................... 53 dc operating characteristics ............................................................ 54 ac characteristics .............................................................................. 55 crystal characteristics ....................................................................... 57 pad layout ......................................................................................... 62 application examples ........................................................................ 65 ordering information .......................................................................... 66 table of contents ............................................................................... 68
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